Module core::arch::riscv64

🔬This is a nightly-only experimental API. (stdsimd #27731)

Available on RISC-V RV64 only.

Platform-specific intrinsics for the riscv64 platform.

See the module documentation for more details.

Functions

fence_i^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Generates the FENCE.I instruction

frcsrExperimentalRISC-V RV32 or RISC-V RV64

Reads the floating-point control and status register fcsr

frflagsExperimentalRISC-V RV32 or RISC-V RV64

Reads the floating-point accrued exception flags register fflags

frrmExperimentalRISC-V RV32 or RISC-V RV64

Reads the floating-point rounding mode register frm

fscsrExperimentalRISC-V RV32 or RISC-V RV64

Swaps the floating-point control and status register fcsr

fsflagsExperimentalRISC-V RV32 or RISC-V RV64

Swaps the floating-point accrued exception flags register fflags

fsrmExperimentalRISC-V RV32 or RISC-V RV64

Swaps the floating-point rounding mode register frm

hfence_gvma^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Hypervisor memory management fence for guest physical address and virtual machine

hfence_gvma_all^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Hypervisor memory management fence for all virtual machines and guest physical addresses

hfence_gvma_gaddr^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Hypervisor memory management fence for guest physical address

hfence_gvma_vmid^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Hypervisor memory management fence for given virtual machine

hfence_vvma^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Hypervisor memory management fence for given guest virtual address and guest address space

hfence_vvma_all^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Hypervisor memory management fence for all guest address spaces and guest virtual addresses

hfence_vvma_asid^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Hypervisor memory management fence for given guest address space

hfence_vvma_vaddr^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Hypervisor memory management fence for given guest virtual address

hinval_gvma^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Invalidate hypervisor translation cache for guest physical address and virtual machine

hinval_gvma_all^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Invalidate hypervisor translation cache for all virtual machines and guest physical addresses

hinval_gvma_gaddr^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Invalidate hypervisor translation cache for guest physical address

hinval_gvma_vmid^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Invalidate hypervisor translation cache for given virtual machine

hinval_vvma^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Invalidate hypervisor translation cache for given guest virtual address and guest address space

hinval_vvma_all^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Invalidate hypervisor translation cache for all guest address spaces and guest virtual addresses

hinval_vvma_asid^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Invalidate hypervisor translation cache for given guest address space

hinval_vvma_vaddr^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Invalidate hypervisor translation cache for given guest virtual address

hlv_b^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Loads virtual machine memory by signed byte integer

hlv_bu^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Loads virtual machine memory by unsigned byte integer

hlv_d^⚠Experimental

Loads virtual machine memory by double integer

hlv_h^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Loads virtual machine memory by signed half integer

hlv_hu^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Loads virtual machine memory by unsigned half integer

hlv_w^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Loads virtual machine memory by signed word integer

hlv_wu^⚠Experimental

Loads virtual machine memory by unsigned word integer

hlvx_hu^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Accesses virtual machine instruction by unsigned half integer

hlvx_wu^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Accesses virtual machine instruction by unsigned word integer

hsv_b^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Stores virtual machine memory by byte integer

hsv_d^⚠Experimental

Stores virtual machine memory by double integer

hsv_h^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Stores virtual machine memory by half integer

hsv_w^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Stores virtual machine memory by word integer

nopExperimentalRISC-V RV32 or RISC-V RV64

Generates the NOP instruction

pauseExperimentalRISC-V RV32 or RISC-V RV64

Generates the PAUSE instruction

sfence_inval_ir^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Generates the SFENCE.INVAL.IR instruction

sfence_vma^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Supervisor memory management fence for given virtual address and address space

sfence_vma_all^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Supervisor memory management fence for all address spaces and virtual addresses

sfence_vma_asid^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Supervisor memory management fence for given address space

sfence_vma_vaddr^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Supervisor memory management fence for given virtual address

sfence_w_inval^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Generates the SFENCE.W.INVAL instruction

sinval_vma^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Invalidate supervisor translation cache for given virtual address and address space

sinval_vma_all^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Invalidate supervisor translation cache for all address spaces and virtual addresses

sinval_vma_asid^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Invalidate supervisor translation cache for given address space

sinval_vma_vaddr^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Invalidate supervisor translation cache for given virtual address

sm3p0ExperimentalRISC-V RV32 or RISC-V RV64

P0 transformation function as is used in the SM3 hash algorithm

sm3p1ExperimentalRISC-V RV32 or RISC-V RV64

P1 transformation function as is used in the SM3 hash algorithm

sm4edExperimentalRISC-V RV32 or RISC-V RV64

Accelerates the round function F in the SM4 block cipher algorithm

sm4ksExperimentalRISC-V RV32 or RISC-V RV64

Accelerates the key schedule operation in the SM4 block cipher algorithm

wfi^⚠ExperimentalRISC-V RV32 or RISC-V RV64

Generates the WFI instruction