🔬This is a nightly-only experimental API. (stdsimd #27731)
Available on RISC-V RV32 only.
Expand description

Platform-specific intrinsics for the riscv32 platform.

See the module documentation for more details.

Functions

fence_iExperimentalRISC-V RV32 or RISC-V RV64
Generates the FENCE.I instruction
frcsrExperimentalRISC-V RV32 or RISC-V RV64
Reads the floating-point control and status register fcsr
frflagsExperimentalRISC-V RV32 or RISC-V RV64
Reads the floating-point accrued exception flags register fflags
frrmExperimentalRISC-V RV32 or RISC-V RV64
Reads the floating-point rounding mode register frm
fscsrExperimentalRISC-V RV32 or RISC-V RV64
Swaps the floating-point control and status register fcsr
fsflagsExperimentalRISC-V RV32 or RISC-V RV64
Swaps the floating-point accrued exception flags register fflags
fsrmExperimentalRISC-V RV32 or RISC-V RV64
Swaps the floating-point rounding mode register frm
hfence_gvmaExperimentalRISC-V RV32 or RISC-V RV64
Hypervisor memory management fence for guest physical address and virtual machine
hfence_gvma_allExperimentalRISC-V RV32 or RISC-V RV64
Hypervisor memory management fence for all virtual machines and guest physical addresses
hfence_gvma_gaddrExperimentalRISC-V RV32 or RISC-V RV64
Hypervisor memory management fence for guest physical address
hfence_gvma_vmidExperimentalRISC-V RV32 or RISC-V RV64
Hypervisor memory management fence for given virtual machine
hfence_vvmaExperimentalRISC-V RV32 or RISC-V RV64
Hypervisor memory management fence for given guest virtual address and guest address space
hfence_vvma_allExperimentalRISC-V RV32 or RISC-V RV64
Hypervisor memory management fence for all guest address spaces and guest virtual addresses
hfence_vvma_asidExperimentalRISC-V RV32 or RISC-V RV64
Hypervisor memory management fence for given guest address space
hfence_vvma_vaddrExperimentalRISC-V RV32 or RISC-V RV64
Hypervisor memory management fence for given guest virtual address
hinval_gvmaExperimentalRISC-V RV32 or RISC-V RV64
Invalidate hypervisor translation cache for guest physical address and virtual machine
hinval_gvma_allExperimentalRISC-V RV32 or RISC-V RV64
Invalidate hypervisor translation cache for all virtual machines and guest physical addresses
hinval_gvma_gaddrExperimentalRISC-V RV32 or RISC-V RV64
Invalidate hypervisor translation cache for guest physical address
hinval_gvma_vmidExperimentalRISC-V RV32 or RISC-V RV64
Invalidate hypervisor translation cache for given virtual machine
hinval_vvmaExperimentalRISC-V RV32 or RISC-V RV64
Invalidate hypervisor translation cache for given guest virtual address and guest address space
hinval_vvma_allExperimentalRISC-V RV32 or RISC-V RV64
Invalidate hypervisor translation cache for all guest address spaces and guest virtual addresses
hinval_vvma_asidExperimentalRISC-V RV32 or RISC-V RV64
Invalidate hypervisor translation cache for given guest address space
hinval_vvma_vaddrExperimentalRISC-V RV32 or RISC-V RV64
Invalidate hypervisor translation cache for given guest virtual address
hlv_bExperimentalRISC-V RV32 or RISC-V RV64
Loads virtual machine memory by signed byte integer
hlv_buExperimentalRISC-V RV32 or RISC-V RV64
Loads virtual machine memory by unsigned byte integer
hlv_hExperimentalRISC-V RV32 or RISC-V RV64
Loads virtual machine memory by signed half integer
hlv_huExperimentalRISC-V RV32 or RISC-V RV64
Loads virtual machine memory by unsigned half integer
hlv_wExperimentalRISC-V RV32 or RISC-V RV64
Loads virtual machine memory by signed word integer
hlvx_huExperimentalRISC-V RV32 or RISC-V RV64
Accesses virtual machine instruction by unsigned half integer
hlvx_wuExperimentalRISC-V RV32 or RISC-V RV64
Accesses virtual machine instruction by unsigned word integer
hsv_bExperimentalRISC-V RV32 or RISC-V RV64
Stores virtual machine memory by byte integer
hsv_hExperimentalRISC-V RV32 or RISC-V RV64
Stores virtual machine memory by half integer
hsv_wExperimentalRISC-V RV32 or RISC-V RV64
Stores virtual machine memory by word integer
nopExperimentalRISC-V RV32 or RISC-V RV64
Generates the NOP instruction
pauseExperimentalRISC-V RV32 or RISC-V RV64
Generates the PAUSE instruction
sfence_inval_irExperimentalRISC-V RV32 or RISC-V RV64
Generates the SFENCE.INVAL.IR instruction
sfence_vmaExperimentalRISC-V RV32 or RISC-V RV64
Supervisor memory management fence for given virtual address and address space
sfence_vma_allExperimentalRISC-V RV32 or RISC-V RV64
Supervisor memory management fence for all address spaces and virtual addresses
sfence_vma_asidExperimentalRISC-V RV32 or RISC-V RV64
Supervisor memory management fence for given address space
sfence_vma_vaddrExperimentalRISC-V RV32 or RISC-V RV64
Supervisor memory management fence for given virtual address
sfence_w_invalExperimentalRISC-V RV32 or RISC-V RV64
Generates the SFENCE.W.INVAL instruction
sinval_vmaExperimentalRISC-V RV32 or RISC-V RV64
Invalidate supervisor translation cache for given virtual address and address space
sinval_vma_allExperimentalRISC-V RV32 or RISC-V RV64
Invalidate supervisor translation cache for all address spaces and virtual addresses
sinval_vma_asidExperimentalRISC-V RV32 or RISC-V RV64
Invalidate supervisor translation cache for given address space
sinval_vma_vaddrExperimentalRISC-V RV32 or RISC-V RV64
Invalidate supervisor translation cache for given virtual address
sm3p0ExperimentalRISC-V RV32 or RISC-V RV64
P0 transformation function as is used in the SM3 hash algorithm
sm3p1ExperimentalRISC-V RV32 or RISC-V RV64
P1 transformation function as is used in the SM3 hash algorithm
sm4edExperimentalRISC-V RV32 or RISC-V RV64
Accelerates the round function F in the SM4 block cipher algorithm
sm4ksExperimentalRISC-V RV32 or RISC-V RV64
Accelerates the key schedule operation in the SM4 block cipher algorithm
wfiExperimentalRISC-V RV32 or RISC-V RV64
Generates the WFI instruction