Module core::arch::aarch64

1.59.0 · source · [−]
Available on AArch64 only.
Expand description

Platform-specific intrinsics for the aarch64 platform.

See the module documentation for more details.

Structs

APSRExperimental
Application Program Status Register
SYExperimental
Full system is the required shareability domain, reads and writes are the required access types
float32x2_tExperimental
ARM-specific 64-bit wide vector of two packed f32.
float32x2x2_tExperimental
ARM-specific type containing two float32x2_t vectors.
float32x2x3_tExperimental
ARM-specific type containing three float32x2_t vectors.
float32x2x4_tExperimental
ARM-specific type containing four float32x2_t vectors.
float32x4_tExperimental
ARM-specific 128-bit wide vector of four packed f32.
float32x4x2_tExperimental
ARM-specific type containing two float32x4_t vectors.
float32x4x3_tExperimental
ARM-specific type containing three float32x4_t vectors.
float32x4x4_tExperimental
ARM-specific type containing four float32x4_t vectors.
int8x8_tExperimental
ARM-specific 64-bit wide vector of eight packed i8.
int8x8x2_tExperimental
ARM-specific type containing two int8x8_t vectors.
int8x8x3_tExperimental
ARM-specific type containing three int8x8_t vectors.
int8x8x4_tExperimental
ARM-specific type containing four int8x8_t vectors.
int8x16_tExperimental
ARM-specific 128-bit wide vector of sixteen packed i8.
int8x16x2_tExperimental
ARM-specific type containing two int8x16_t vectors.
int8x16x3_tExperimental
ARM-specific type containing three int8x16_t vectors.
int8x16x4_tExperimental
ARM-specific type containing four int8x16_t vectors.
int16x4_tExperimental
ARM-specific 64-bit wide vector of four packed i16.
int16x4x2_tExperimental
ARM-specific type containing two int16x4_t vectors.
int16x4x3_tExperimental
ARM-specific type containing three int16x4_t vectors.
int16x4x4_tExperimental
ARM-specific type containing four int16x4_t vectors.
int16x8_tExperimental
ARM-specific 128-bit wide vector of eight packed i16.
int16x8x2_tExperimental
ARM-specific type containing two int16x8_t vectors.
int16x8x3_tExperimental
ARM-specific type containing three int16x8_t vectors.
int16x8x4_tExperimental
ARM-specific type containing four int16x8_t vectors.
int32x2_tExperimental
ARM-specific 64-bit wide vector of two packed i32.
int32x2x2_tExperimental
ARM-specific type containing two int32x2_t vectors.
int32x2x3_tExperimental
ARM-specific type containing three int32x2_t vectors.
int32x2x4_tExperimental
ARM-specific type containing four int32x2_t vectors.
int32x4_tExperimental
ARM-specific 128-bit wide vector of four packed i32.
int32x4x2_tExperimental
ARM-specific type containing two int32x4_t vectors.
int32x4x3_tExperimental
ARM-specific type containing three int32x4_t vectors.
int32x4x4_tExperimental
ARM-specific type containing four int32x4_t vectors.
int64x1_tExperimental
ARM-specific 64-bit wide vector of one packed i64.
int64x1x2_tExperimental
ARM-specific type containing four int64x1_t vectors.
int64x1x3_tExperimental
ARM-specific type containing four int64x1_t vectors.
int64x1x4_tExperimental
ARM-specific type containing four int64x1_t vectors.
int64x2_tExperimental
ARM-specific 128-bit wide vector of two packed i64.
int64x2x2_tExperimental
ARM-specific type containing four int64x2_t vectors.
int64x2x3_tExperimental
ARM-specific type containing four int64x2_t vectors.
int64x2x4_tExperimental
ARM-specific type containing four int64x2_t vectors.
poly8x8_tExperimental
ARM-specific 64-bit wide polynomial vector of eight packed p8.
poly8x8x2_tExperimental
ARM-specific type containing two poly8x8_t vectors.
poly8x8x3_tExperimental
ARM-specific type containing three poly8x8_t vectors.
poly8x8x4_tExperimental
ARM-specific type containing four poly8x8_t vectors.
poly8x16_tExperimental
ARM-specific 128-bit wide vector of sixteen packed p8.
poly8x16x2_tExperimental
ARM-specific type containing two poly8x16_t vectors.
poly8x16x3_tExperimental
ARM-specific type containing three poly8x16_t vectors.
poly8x16x4_tExperimental
ARM-specific type containing four poly8x16_t vectors.
poly16x4_tExperimental
ARM-specific 64-bit wide vector of four packed p16.
poly16x4x2_tExperimental
ARM-specific type containing two poly16x4_t vectors.
poly16x4x3_tExperimental
ARM-specific type containing three poly16x4_t vectors.
poly16x4x4_tExperimental
ARM-specific type containing four poly16x4_t vectors.
poly16x8_tExperimental
ARM-specific 128-bit wide vector of eight packed p16.
poly16x8x2_tExperimental
ARM-specific type containing two poly16x8_t vectors.
poly16x8x3_tExperimental
ARM-specific type containing three poly16x8_t vectors.
poly16x8x4_tExperimental
ARM-specific type containing four poly16x8_t vectors.
poly64x1_tExperimental
ARM-specific 64-bit wide vector of one packed p64.
poly64x1x2_tExperimental
ARM-specific type containing four poly64x1_t vectors.
poly64x1x3_tExperimental
ARM-specific type containing four poly64x1_t vectors.
poly64x1x4_tExperimental
ARM-specific type containing four poly64x1_t vectors.
poly64x2_tExperimental
ARM-specific 128-bit wide vector of two packed p64.
poly64x2x2_tExperimental
ARM-specific type containing four poly64x2_t vectors.
poly64x2x3_tExperimental
ARM-specific type containing four poly64x2_t vectors.
poly64x2x4_tExperimental
ARM-specific type containing four poly64x2_t vectors.
uint8x8_tExperimental
ARM-specific 64-bit wide vector of eight packed u8.
uint8x8x2_tExperimental
ARM-specific type containing two uint8x8_t vectors.
uint8x8x3_tExperimental
ARM-specific type containing three uint8x8_t vectors.
uint8x8x4_tExperimental
ARM-specific type containing four uint8x8_t vectors.
uint8x16_tExperimental
ARM-specific 128-bit wide vector of sixteen packed u8.
uint8x16x2_tExperimental
ARM-specific type containing two uint8x16_t vectors.
uint8x16x3_tExperimental
ARM-specific type containing three uint8x16_t vectors.
uint8x16x4_tExperimental
ARM-specific type containing four uint8x16_t vectors.
uint16x4_tExperimental
ARM-specific 64-bit wide vector of four packed u16.
uint16x4x2_tExperimental
ARM-specific type containing two uint16x4_t vectors.
uint16x4x3_tExperimental
ARM-specific type containing three uint16x4_t vectors.
uint16x4x4_tExperimental
ARM-specific type containing four uint16x4_t vectors.
uint16x8_tExperimental
ARM-specific 128-bit wide vector of eight packed u16.
uint16x8x2_tExperimental
ARM-specific type containing two uint16x8_t vectors.
uint16x8x3_tExperimental
ARM-specific type containing three uint16x8_t vectors.
uint16x8x4_tExperimental
ARM-specific type containing four uint16x8_t vectors.
uint32x2_tExperimental
ARM-specific 64-bit wide vector of two packed u32.
uint32x2x2_tExperimental
ARM-specific type containing two uint32x2_t vectors.
uint32x2x3_tExperimental
ARM-specific type containing three uint32x2_t vectors.
uint32x2x4_tExperimental
ARM-specific type containing four uint32x2_t vectors.
uint32x4_tExperimental
ARM-specific 128-bit wide vector of four packed u32.
uint32x4x2_tExperimental
ARM-specific type containing two uint32x4_t vectors.
uint32x4x3_tExperimental
ARM-specific type containing three uint32x4_t vectors.
uint32x4x4_tExperimental
ARM-specific type containing four uint32x4_t vectors.
uint64x1_tExperimental
ARM-specific 64-bit wide vector of one packed u64.
uint64x1x2_tExperimental
ARM-specific type containing four uint64x1_t vectors.
uint64x1x3_tExperimental
ARM-specific type containing four uint64x1_t vectors.
uint64x1x4_tExperimental
ARM-specific type containing four uint64x1_t vectors.
uint64x2_tExperimental
ARM-specific 128-bit wide vector of two packed u64.
uint64x2x2_tExperimental
ARM-specific type containing four uint64x2_t vectors.
uint64x2x3_tExperimental
ARM-specific type containing four uint64x2_t vectors.
uint64x2x4_tExperimental
ARM-specific type containing four uint64x2_t vectors.
float64x1_t
ARM-specific 64-bit wide vector of one packed f64.
float64x1x2_t
ARM-specific type containing two float64x1_t vectors.
float64x1x3_t
ARM-specific type containing three float64x1_t vectors.
float64x1x4_t
ARM-specific type containing four float64x1_t vectors.
float64x2_t
ARM-specific 128-bit wide vector of two packed f64.
float64x2x2_t
ARM-specific type containing two float64x2_t vectors.
float64x2x3_t
ARM-specific type containing three float64x2_t vectors.
float64x2x4_t
ARM-specific type containing four float64x2_t vectors.

Constants

_PREFETCH_LOCALITY0Experimental
See prefetch.
_PREFETCH_LOCALITY1Experimental
See prefetch.
_PREFETCH_LOCALITY2Experimental
See prefetch.
_PREFETCH_LOCALITY3Experimental
See prefetch.
_PREFETCH_READExperimental
See prefetch.
_PREFETCH_WRITEExperimental
See prefetch.
_TMFAILURE_CNCLExperimental
Transaction executed a TCANCEL instruction
_TMFAILURE_DBGExperimental
Transaction aborted due to a debug trap.
_TMFAILURE_ERRExperimental
Transaction aborted because a non-permissible operation was attempted
_TMFAILURE_IMPExperimental
Fallback error type for any other reason
_TMFAILURE_INTExperimental
Transaction failed from interrupt
_TMFAILURE_MEMExperimental
Transaction aborted because a conflict occurred
_TMFAILURE_NESTExperimental
Transaction aborted due to transactional nesting level was exceeded
_TMFAILURE_REASONExperimental
Extraction mask for failure reason
_TMFAILURE_RTRYExperimental
Transaction retry is possible.
_TMFAILURE_SIZEExperimental
Transaction aborted due to read or write set limit was exceeded
_TMFAILURE_TRIVIALExperimental
Indicates a TRIVIAL version of TM is available
_TMSTART_SUCCESSExperimental
Transaction successfully started.

Functions

__breakpoint⚠Experimental
Inserts a breakpoint instruction.
__crc32b⚠Experimentalcrc
CRC32 single round checksum for bytes (8 bits).
__crc32cb⚠Experimentalcrc
CRC32-C single round checksum for bytes (8 bits).
__crc32cd⚠Experimentalcrc
CRC32-C single round checksum for quad words (64 bits).
__crc32ch⚠Experimentalcrc
CRC32-C single round checksum for half words (16 bits).
__crc32cw⚠Experimentalcrc
CRC32-C single round checksum for words (32 bits).
__crc32d⚠Experimentalcrc
CRC32 single round checksum for quad words (64 bits).
__crc32h⚠Experimentalcrc
CRC32 single round checksum for half words (16 bits).
__crc32w⚠Experimentalcrc
CRC32 single round checksum for words (32 bits).
__dmb⚠Experimental
Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction.
__dsb⚠Experimental
Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction.
__isb⚠Experimental
Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction.
__nop⚠Experimental
Generates an unspecified no-op instruction.
__rsr⚠Experimental
Reads a 32-bit system register
__rsrp⚠Experimental
Reads a system register containing an address
__sev⚠Experimental
Generates a SEV (send a global event) hint instruction.
__sevl⚠Experimental
Generates a send a local event hint instruction.
__tcancel⚠Experimentaltme
Cancels the current transaction and discards all state modifications that were performed transactionally.
__tcommit⚠Experimentaltme
Commits the current transaction. For a nested transaction, the only effect is that the transactional nesting depth is decreased. For an outer transaction, the state modifications performed transactionally are committed to the architectural state.
__tstart⚠Experimentaltme
Starts a new transaction. When the transaction starts successfully the return value is 0. If the transaction fails, all state modifications are discarded and a cause of the failure is encoded in the return value.
__ttest⚠Experimentaltme
Tests if executing inside a transaction. If no transaction is currently executing, the return value is 0. Otherwise, this intrinsic returns the depth of the transaction.
__wfe⚠Experimental
Generates a WFE (wait for event) hint instruction, or nothing.
__wfi⚠Experimental
Generates a WFI (wait for interrupt) hint instruction, or nothing.
__wsr⚠Experimental
Writes a 32-bit system register
__wsrp⚠Experimental
Writes a system register containing an address
__yield⚠Experimental
Generates a YIELD hint instruction.
_cls_u32⚠Experimental
Counts the leading most significant bits set.
_cls_u64⚠Experimental
Counts the leading most significant bits set.
_clz_u64⚠Experimental
Count Leading Zeros.
_prefetch⚠Experimental
Fetch the cache line that contains address p using the given RW and LOCALITY.
_rbit_u64⚠Experimental
Reverse the bit order.
_rev_u64⚠Experimental
Reverse the order of the bytes.
brk⚠Experimental
Generates the trap instruction BRK 1
vaba_s8⚠Experimentalneon
vaba_s16⚠Experimentalneon
vaba_s32⚠Experimentalneon
vaba_u8⚠Experimentalneon
vaba_u16⚠Experimentalneon
vaba_u32⚠Experimentalneon
vabal_s8⚠Experimentalneon
Signed Absolute difference and Accumulate Long
vabal_s16⚠Experimentalneon
Signed Absolute difference and Accumulate Long
vabal_s32⚠Experimentalneon
Signed Absolute difference and Accumulate Long
vabal_u8⚠Experimentalneon
Unsigned Absolute difference and Accumulate Long
vabal_u16⚠Experimentalneon
Unsigned Absolute difference and Accumulate Long
vabal_u32⚠Experimentalneon
Unsigned Absolute difference and Accumulate Long
vabaq_s8⚠Experimentalneon
vabaq_s16⚠Experimentalneon
vabaq_s32⚠Experimentalneon
vabaq_u8⚠Experimentalneon
vabaq_u16⚠Experimentalneon
vabaq_u32⚠Experimentalneon
vabd_f32⚠Experimentalneon
Absolute difference between the arguments of Floating
vabd_s8⚠Experimentalneon
Absolute difference between the arguments
vabd_s16⚠Experimentalneon
Absolute difference between the arguments
vabd_s32⚠Experimentalneon
Absolute difference between the arguments
vabd_u8⚠Experimentalneon
Absolute difference between the arguments
vabd_u16⚠Experimentalneon
Absolute difference between the arguments
vabd_u32⚠Experimentalneon
Absolute difference between the arguments
vabdl_s8⚠Experimentalneon
Signed Absolute difference Long
vabdl_s16⚠Experimentalneon
Signed Absolute difference Long
vabdl_s32⚠Experimentalneon
Signed Absolute difference Long
vabdl_u8⚠Experimentalneon
Unsigned Absolute difference Long
vabdl_u16⚠Experimentalneon
Unsigned Absolute difference Long
vabdl_u32⚠Experimentalneon
Unsigned Absolute difference Long
vabdq_f32⚠Experimentalneon
Absolute difference between the arguments of Floating
vabdq_s8⚠Experimentalneon
Absolute difference between the arguments
vabdq_s16⚠Experimentalneon
Absolute difference between the arguments
vabdq_s32⚠Experimentalneon
Absolute difference between the arguments
vabdq_u8⚠Experimentalneon
Absolute difference between the arguments
vabdq_u16⚠Experimentalneon
Absolute difference between the arguments
vabdq_u32⚠Experimentalneon
Absolute difference between the arguments
vabs_f32⚠Experimentalneon
Floating-point absolute value
vabs_s8⚠Experimentalneon
Absolute value (wrapping).
vabs_s16⚠Experimentalneon
Absolute value (wrapping).
vabs_s32⚠Experimentalneon
Absolute value (wrapping).
vabsq_f32⚠Experimentalneon
Floating-point absolute value
vabsq_s8⚠Experimentalneon
Absolute value (wrapping).
vabsq_s16⚠Experimentalneon
Absolute value (wrapping).
vabsq_s32⚠Experimentalneon
Absolute value (wrapping).
vadd_f32⚠Experimentalneon
Vector add.
vadd_p8⚠Experimentalneon
Bitwise exclusive OR
vadd_p16⚠Experimentalneon
Bitwise exclusive OR
vadd_p64⚠Experimentalneon
Bitwise exclusive OR
vadd_s8⚠Experimentalneon
Vector add.
vadd_s16⚠Experimentalneon
Vector add.
vadd_s32⚠Experimentalneon
Vector add.
vadd_u8⚠Experimentalneon
Vector add.
vadd_u16⚠Experimentalneon
Vector add.
vadd_u32⚠Experimentalneon
Vector add.
vaddhn_high_s16⚠Experimentalneon
Add returning High Narrow (high half).
vaddhn_high_s32⚠Experimentalneon
Add returning High Narrow (high half).
vaddhn_high_s64⚠Experimentalneon
Add returning High Narrow (high half).
vaddhn_high_u16⚠Experimentalneon
Add returning High Narrow (high half).
vaddhn_high_u32⚠Experimentalneon
Add returning High Narrow (high half).
vaddhn_high_u64⚠Experimentalneon
Add returning High Narrow (high half).
vaddhn_s16⚠Experimentalneon
Add returning High Narrow.
vaddhn_s32⚠Experimentalneon
Add returning High Narrow.
vaddhn_s64⚠Experimentalneon
Add returning High Narrow.
vaddhn_u16⚠Experimentalneon
Add returning High Narrow.
vaddhn_u32⚠Experimentalneon
Add returning High Narrow.
vaddhn_u64⚠Experimentalneon
Add returning High Narrow.
vaddl_high_s8⚠Experimentalneon
Signed Add Long (vector, high half).
vaddl_high_s16⚠Experimentalneon
Signed Add Long (vector, high half).
vaddl_high_s32⚠Experimentalneon
Signed Add Long (vector, high half).
vaddl_high_u8⚠Experimentalneon
Unsigned Add Long (vector, high half).
vaddl_high_u16⚠Experimentalneon
Unsigned Add Long (vector, high half).
vaddl_high_u32⚠Experimentalneon
Unsigned Add Long (vector, high half).
vaddl_s8⚠Experimentalneon
Signed Add Long (vector).
vaddl_s16⚠Experimentalneon
Signed Add Long (vector).
vaddl_s32⚠Experimentalneon
Signed Add Long (vector).
vaddl_u8⚠Experimentalneon
Unsigned Add Long (vector).
vaddl_u16⚠Experimentalneon
Unsigned Add Long (vector).
vaddl_u32⚠Experimentalneon
Unsigned Add Long (vector).
vaddq_f32⚠Experimentalneon
Vector add.
vaddq_p8⚠Experimentalneon
Bitwise exclusive OR
vaddq_p16⚠Experimentalneon
Bitwise exclusive OR
vaddq_p64⚠Experimentalneon
Bitwise exclusive OR
vaddq_p128⚠Experimentalneon
Bitwise exclusive OR
vaddq_s8⚠Experimentalneon
Vector add.
vaddq_s16⚠Experimentalneon
Vector add.
vaddq_s32⚠Experimentalneon
Vector add.
vaddq_s64⚠Experimentalneon
Vector add.
vaddq_u8⚠Experimentalneon
Vector add.
vaddq_u16⚠Experimentalneon
Vector add.
vaddq_u32⚠Experimentalneon
Vector add.
vaddq_u64⚠Experimentalneon
Vector add.
vaddw_high_s8⚠Experimentalneon
Signed Add Wide (high half).
vaddw_high_s16⚠Experimentalneon
Signed Add Wide (high half).
vaddw_high_s32⚠Experimentalneon
Signed Add Wide (high half).
vaddw_high_u8⚠Experimentalneon
Unsigned Add Wide (high half).
vaddw_high_u16⚠Experimentalneon
Unsigned Add Wide (high half).
vaddw_high_u32⚠Experimentalneon
Unsigned Add Wide (high half).
vaddw_s8⚠Experimentalneon
Signed Add Wide.
vaddw_s16⚠Experimentalneon
Signed Add Wide.
vaddw_s32⚠Experimentalneon
Signed Add Wide.
vaddw_u8⚠Experimentalneon
Unsigned Add Wide.
vaddw_u16⚠Experimentalneon
Unsigned Add Wide.
vaddw_u32⚠Experimentalneon
Unsigned Add Wide.
vaesdq_u8⚠Experimentalaes
AES single round decryption.
vaeseq_u8⚠Experimentalaes
AES single round encryption.
vaesimcq_u8⚠Experimentalaes
AES inverse mix columns.
vaesmcq_u8⚠Experimentalaes
AES mix columns.
vand_s8⚠Experimentalneon
Vector bitwise and
vand_s16⚠Experimentalneon
Vector bitwise and
vand_s32⚠Experimentalneon
Vector bitwise and
vand_s64⚠Experimentalneon
Vector bitwise and
vand_u8⚠Experimentalneon
Vector bitwise and
vand_u16⚠Experimentalneon
Vector bitwise and
vand_u32⚠Experimentalneon
Vector bitwise and
vand_u64⚠Experimentalneon
Vector bitwise and
vandq_s8⚠Experimentalneon
Vector bitwise and
vandq_s16⚠Experimentalneon
Vector bitwise and
vandq_s32⚠Experimentalneon
Vector bitwise and
vandq_s64⚠Experimentalneon
Vector bitwise and
vandq_u8⚠Experimentalneon
Vector bitwise and
vandq_u16⚠Experimentalneon
Vector bitwise and
vandq_u32⚠Experimentalneon
Vector bitwise and
vandq_u64⚠Experimentalneon
Vector bitwise and
vbcaxq_s8⚠Experimentalneon,sha3
Bit clear and exclusive OR
vbcaxq_s16⚠Experimentalneon,sha3
Bit clear and exclusive OR
vbcaxq_s32⚠Experimentalneon,sha3
Bit clear and exclusive OR
vbcaxq_s64⚠Experimentalneon,sha3
Bit clear and exclusive OR
vbcaxq_u8⚠Experimentalneon,sha3
Bit clear and exclusive OR
vbcaxq_u16⚠Experimentalneon,sha3
Bit clear and exclusive OR
vbcaxq_u32⚠Experimentalneon,sha3
Bit clear and exclusive OR
vbcaxq_u64⚠Experimentalneon,sha3
Bit clear and exclusive OR
vbic_s8⚠Experimentalneon
Vector bitwise bit clear
vbic_s16⚠Experimentalneon
Vector bitwise bit clear
vbic_s32⚠Experimentalneon
Vector bitwise bit clear
vbic_s64⚠Experimentalneon
Vector bitwise bit clear
vbic_u8⚠Experimentalneon
Vector bitwise bit clear
vbic_u16⚠Experimentalneon
Vector bitwise bit clear
vbic_u32⚠Experimentalneon
Vector bitwise bit clear
vbic_u64⚠Experimentalneon
Vector bitwise bit clear
vbicq_s8⚠Experimentalneon
Vector bitwise bit clear
vbicq_s16⚠Experimentalneon
Vector bitwise bit clear
vbicq_s32⚠Experimentalneon
Vector bitwise bit clear
vbicq_s64⚠Experimentalneon
Vector bitwise bit clear
vbicq_u8⚠Experimentalneon
Vector bitwise bit clear
vbicq_u16⚠Experimentalneon
Vector bitwise bit clear
vbicq_u32⚠Experimentalneon
Vector bitwise bit clear
vbicq_u64⚠Experimentalneon
Vector bitwise bit clear
vbsl_f32⚠Experimentalneon
Bitwise Select.
vbsl_p8⚠Experimentalneon
Bitwise Select.
vbsl_p16⚠Experimentalneon
Bitwise Select.
vbsl_s8⚠Experimentalneon
Bitwise Select instructions. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register. Bitwise Select.
vbsl_s16⚠Experimentalneon
Bitwise Select.
vbsl_s32⚠Experimentalneon
Bitwise Select.
vbsl_s64⚠Experimentalneon
Bitwise Select.
vbsl_u8⚠Experimentalneon
Bitwise Select.
vbsl_u16⚠Experimentalneon
Bitwise Select.
vbsl_u32⚠Experimentalneon
Bitwise Select.
vbsl_u64⚠Experimentalneon
Bitwise Select.
vbslq_f32⚠Experimentalneon
Bitwise Select. (128-bit)
vbslq_p8⚠Experimentalneon
Bitwise Select. (128-bit)
vbslq_p16⚠Experimentalneon
Bitwise Select. (128-bit)
vbslq_s8⚠Experimentalneon
Bitwise Select. (128-bit)
vbslq_s16⚠Experimentalneon
Bitwise Select. (128-bit)
vbslq_s32⚠Experimentalneon
Bitwise Select. (128-bit)
vbslq_s64⚠Experimentalneon
Bitwise Select. (128-bit)
vbslq_u8⚠Experimentalneon
Bitwise Select. (128-bit)
vbslq_u16⚠Experimentalneon
Bitwise Select. (128-bit)
vbslq_u32⚠Experimentalneon
Bitwise Select. (128-bit)
vbslq_u64⚠Experimentalneon
Bitwise Select. (128-bit)
vcadd_rot90_f32⚠Experimentalneon,fcma
Floating-point complex add
vcadd_rot270_f32⚠Experimentalneon,fcma
Floating-point complex add
vcaddq_rot90_f32⚠Experimentalneon,fcma
Floating-point complex add
vcaddq_rot90_f64⚠Experimentalneon,fcma
Floating-point complex add
vcaddq_rot270_f32⚠Experimentalneon,fcma
Floating-point complex add
vcaddq_rot270_f64⚠Experimentalneon,fcma
Floating-point complex add
vcage_f32⚠Experimentalneon
Floating-point absolute compare greater than or equal
vcageq_f32⚠Experimentalneon
Floating-point absolute compare greater than or equal
vcagt_f32⚠Experimentalneon
Floating-point absolute compare greater than
vcagtq_f32⚠Experimentalneon
Floating-point absolute compare greater than
vcale_f32⚠Experimentalneon
Floating-point absolute compare less than or equal
vcaleq_f32⚠Experimentalneon
Floating-point absolute compare less than or equal
vcalt_f32⚠Experimentalneon
Floating-point absolute compare less than
vcaltq_f32⚠Experimentalneon
Floating-point absolute compare less than
vceq_f32⚠Experimentalneon
Floating-point compare equal
vceq_p8⚠Experimentalneon
Compare bitwise Equal (vector)
vceq_s8⚠Experimentalneon
Compare bitwise Equal (vector)
vceq_s16⚠Experimentalneon
Compare bitwise Equal (vector)
vceq_s32⚠Experimentalneon
Compare bitwise Equal (vector)
vceq_u8⚠Experimentalneon
Compare bitwise Equal (vector)
vceq_u16⚠Experimentalneon
Compare bitwise Equal (vector)
vceq_u32⚠Experimentalneon
Compare bitwise Equal (vector)
vceqq_f32⚠Experimentalneon
Floating-point compare equal
vceqq_p8⚠Experimentalneon
Compare bitwise Equal (vector)
vceqq_s8⚠Experimentalneon
Compare bitwise Equal (vector)
vceqq_s16⚠Experimentalneon
Compare bitwise Equal (vector)
vceqq_s32⚠Experimentalneon
Compare bitwise Equal (vector)
vceqq_u8⚠Experimentalneon
Compare bitwise Equal (vector)
vceqq_u16⚠Experimentalneon
Compare bitwise Equal (vector)
vceqq_u32⚠Experimentalneon
Compare bitwise Equal (vector)
vcge_f32⚠Experimentalneon
Floating-point compare greater than or equal
vcge_s8⚠Experimentalneon
Compare signed greater than or equal
vcge_s16⚠Experimentalneon
Compare signed greater than or equal
vcge_s32⚠Experimentalneon
Compare signed greater than or equal
vcge_u8⚠Experimentalneon
Compare unsigned greater than or equal
vcge_u16⚠Experimentalneon
Compare unsigned greater than or equal
vcge_u32⚠Experimentalneon
Compare unsigned greater than or equal
vcgeq_f32⚠Experimentalneon
Floating-point compare greater than or equal
vcgeq_s8⚠Experimentalneon
Compare signed greater than or equal
vcgeq_s16⚠Experimentalneon
Compare signed greater than or equal
vcgeq_s32⚠Experimentalneon
Compare signed greater than or equal
vcgeq_u8⚠Experimentalneon
Compare unsigned greater than or equal
vcgeq_u16⚠Experimentalneon
Compare unsigned greater than or equal
vcgeq_u32⚠Experimentalneon
Compare unsigned greater than or equal
vcgt_f32⚠Experimentalneon
Floating-point compare greater than
vcgt_s8⚠Experimentalneon
Compare signed greater than
vcgt_s16⚠Experimentalneon
Compare signed greater than
vcgt_s32⚠Experimentalneon
Compare signed greater than
vcgt_u8⚠Experimentalneon
Compare unsigned highe
vcgt_u16⚠Experimentalneon
Compare unsigned highe
vcgt_u32⚠Experimentalneon
Compare unsigned highe
vcgtq_f32⚠Experimentalneon
Floating-point compare greater than
vcgtq_s8⚠Experimentalneon
Compare signed greater than
vcgtq_s16⚠Experimentalneon
Compare signed greater than
vcgtq_s32⚠Experimentalneon
Compare signed greater than
vcgtq_u8⚠Experimentalneon
Compare unsigned highe
vcgtq_u16⚠Experimentalneon
Compare unsigned highe
vcgtq_u32⚠Experimentalneon
Compare unsigned highe
vcle_f32⚠Experimentalneon
Floating-point compare less than or equal
vcle_s8⚠Experimentalneon
Compare signed less than or equal
vcle_s16⚠Experimentalneon
Compare signed less than or equal
vcle_s32⚠Experimentalneon
Compare signed less than or equal
vcle_u8⚠Experimentalneon
Compare unsigned less than or equal
vcle_u16⚠Experimentalneon
Compare unsigned less than or equal
vcle_u32⚠Experimentalneon
Compare unsigned less than or equal
vcleq_f32⚠Experimentalneon
Floating-point compare less than or equal
vcleq_s8⚠Experimentalneon
Compare signed less than or equal
vcleq_s16⚠Experimentalneon
Compare signed less than or equal
vcleq_s32⚠Experimentalneon
Compare signed less than or equal
vcleq_u8⚠Experimentalneon
Compare unsigned less than or equal
vcleq_u16⚠Experimentalneon
Compare unsigned less than or equal
vcleq_u32⚠Experimentalneon
Compare unsigned less than or equal
vcls_s8⚠Experimentalneon
Count leading sign bits
vcls_s16⚠Experimentalneon
Count leading sign bits
vcls_s32⚠Experimentalneon
Count leading sign bits
vcls_u8⚠Experimentalneon
Count leading sign bits
vcls_u16⚠Experimentalneon
Count leading sign bits
vcls_u32⚠Experimentalneon
Count leading sign bits
vclsq_s8⚠Experimentalneon
Count leading sign bits
vclsq_s16⚠Experimentalneon
Count leading sign bits
vclsq_s32⚠Experimentalneon
Count leading sign bits
vclsq_u8⚠Experimentalneon
Count leading sign bits
vclsq_u16⚠Experimentalneon
Count leading sign bits
vclsq_u32⚠Experimentalneon
Count leading sign bits
vclt_f32⚠Experimentalneon
Floating-point compare less than
vclt_s8⚠Experimentalneon
Compare signed less than
vclt_s16⚠Experimentalneon
Compare signed less than
vclt_s32⚠Experimentalneon
Compare signed less than
vclt_u8⚠Experimentalneon
Compare unsigned less than
vclt_u16⚠Experimentalneon
Compare unsigned less than
vclt_u32⚠Experimentalneon
Compare unsigned less than
vcltq_f32⚠Experimentalneon
Floating-point compare less than
vcltq_s8⚠Experimentalneon
Compare signed less than
vcltq_s16⚠Experimentalneon
Compare signed less than
vcltq_s32⚠Experimentalneon
Compare signed less than
vcltq_u8⚠Experimentalneon
Compare unsigned less than
vcltq_u16⚠Experimentalneon
Compare unsigned less than
vcltq_u32⚠Experimentalneon
Compare unsigned less than
vclz_s8⚠Experimentalneon
Count leading zero bits
vclz_s16⚠Experimentalneon
Count leading zero bits
vclz_s32⚠Experimentalneon
Count leading zero bits
vclz_u8⚠Experimentalneon
Count leading zero bits
vclz_u16⚠Experimentalneon
Count leading zero bits
vclz_u32⚠Experimentalneon
Count leading zero bits
vclzq_s8⚠Experimentalneon
Count leading zero bits
vclzq_s16⚠Experimentalneon
Count leading zero bits
vclzq_s32⚠Experimentalneon
Count leading zero bits
vclzq_u8⚠Experimentalneon
Count leading zero bits
vclzq_u16⚠Experimentalneon
Count leading zero bits
vclzq_u32⚠Experimentalneon
Count leading zero bits
vcmla_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_lane_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_laneq_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot90_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot90_lane_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot90_laneq_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot180_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot180_lane_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot180_laneq_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot270_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot270_lane_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmla_rot270_laneq_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_f64⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_lane_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_laneq_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot90_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot90_f64⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot90_lane_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot90_laneq_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot180_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot180_f64⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot180_lane_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot180_laneq_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot270_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot270_f64⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot270_lane_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcmlaq_rot270_laneq_f32⚠Experimentalneon,fcma
Floating-point complex multiply accumulate
vcnt_p8⚠Experimentalneon
Population count per byte.
vcnt_s8⚠Experimentalneon
Population count per byte.
vcnt_u8⚠Experimentalneon
Population count per byte.
vcntq_p8⚠Experimentalneon
Population count per byte.
vcntq_s8⚠Experimentalneon
Population count per byte.
vcntq_u8⚠Experimentalneon
Population count per byte.
vcreate_f32⚠Experimentalneon
Insert vector element from another vector element
vcreate_p8⚠Experimentalneon
Insert vector element from another vector element
vcreate_p16⚠Experimentalneon
Insert vector element from another vector element
vcreate_p64⚠Experimentalneon,aes
Insert vector element from another vector element
vcreate_s8⚠Experimentalneon
Insert vector element from another vector element
vcreate_s16⚠Experimentalneon
Insert vector element from another vector element
vcreate_s32⚠Experimentalneon
Insert vector element from another vector element
vcreate_s64⚠Experimentalneon
Insert vector element from another vector element
vcreate_u8⚠Experimentalneon
Insert vector element from another vector element
vcreate_u16⚠Experimentalneon
Insert vector element from another vector element
vcreate_u32⚠Experimentalneon
Insert vector element from another vector element
vcreate_u64⚠Experimentalneon
Insert vector element from another vector element
vcvt_f32_s32⚠Experimentalneon
Fixed-point convert to floating-point
vcvt_f32_u32⚠Experimentalneon
Fixed-point convert to floating-point
vcvt_s32_f32⚠Experimentalneon
Floating-point convert to signed fixed-point, rounding toward zero
vcvt_u32_f32⚠Experimentalneon
Floating-point convert to unsigned fixed-point, rounding toward zero
vcvtq_f32_s32⚠Experimentalneon
Fixed-point convert to floating-point
vcvtq_f32_u32⚠Experimentalneon
Fixed-point convert to floating-point
vcvtq_s32_f32⚠Experimentalneon
Floating-point convert to signed fixed-point, rounding toward zero
vcvtq_u32_f32⚠Experimentalneon
Floating-point convert to unsigned fixed-point, rounding toward zero
vdot_lane_s32⚠Experimentalneon,dotprod
Dot product arithmetic
vdot_lane_u32⚠Experimentalneon,dotprod
Dot product arithmetic
vdot_laneq_s32⚠Experimentalneon,dotprod
Dot product arithmetic
vdot_laneq_u32⚠Experimentalneon,dotprod
Dot product arithmetic
vdot_s32⚠Experimentalneon,dotprod
Dot product arithmetic
vdot_u32⚠Experimentalneon,dotprod
Dot product arithmetic
vdotq_lane_s32⚠Experimentalneon,dotprod
Dot product arithmetic
vdotq_lane_u32⚠Experimentalneon,dotprod
Dot product arithmetic
vdotq_laneq_s32⚠Experimentalneon,dotprod
Dot product arithmetic
vdotq_laneq_u32⚠Experimentalneon,dotprod
Dot product arithmetic
vdotq_s32⚠Experimentalneon,dotprod
Dot product arithmetic
vdotq_u32⚠Experimentalneon,dotprod
Dot product arithmetic
vdup_lane_f32⚠Experimentalneon
Set all vector lanes to the same value
vdup_lane_p8⚠Experimentalneon
Set all vector lanes to the same value
vdup_lane_p16⚠Experimentalneon
Set all vector lanes to the same value
vdup_lane_s8⚠Experimentalneon
Set all vector lanes to the same value
vdup_lane_s16⚠Experimentalneon
Set all vector lanes to the same value
vdup_lane_s32⚠Experimentalneon
Set all vector lanes to the same value
vdup_lane_s64⚠Experimentalneon
Set all vector lanes to the same value
vdup_lane_u8⚠Experimentalneon
Set all vector lanes to the same value
vdup_lane_u16⚠Experimentalneon
Set all vector lanes to the same value
vdup_lane_u32⚠Experimentalneon
Set all vector lanes to the same value
vdup_lane_u64⚠Experimentalneon
Set all vector lanes to the same value
vdup_laneq_f32⚠Experimentalneon
Set all vector lanes to the same value
vdup_laneq_p8⚠Experimentalneon
Set all vector lanes to the same value
vdup_laneq_p16⚠Experimentalneon
Set all vector lanes to the same value
vdup_laneq_s8⚠Experimentalneon
Set all vector lanes to the same value
vdup_laneq_s16⚠Experimentalneon
Set all vector lanes to the same value
vdup_laneq_s32⚠Experimentalneon
Set all vector lanes to the same value
vdup_laneq_s64⚠Experimentalneon
Set all vector lanes to the same value
vdup_laneq_u8⚠Experimentalneon
Set all vector lanes to the same value
vdup_laneq_u16⚠Experimentalneon
Set all vector lanes to the same value
vdup_laneq_u32⚠Experimentalneon
Set all vector lanes to the same value
vdup_laneq_u64⚠Experimentalneon
Set all vector lanes to the same value
vdup_n_f32⚠Experimentalneon
Duplicate vector element to vector or scalar
vdup_n_p8⚠Experimentalneon
Duplicate vector element to vector or scalar
vdup_n_p16⚠Experimentalneon
Duplicate vector element to vector or scalar
vdup_n_s8⚠Experimentalneon
Duplicate vector element to vector or scalar
vdup_n_s16⚠Experimentalneon
Duplicate vector element to vector or scalar
vdup_n_s32⚠Experimentalneon
Duplicate vector element to vector or scalar
vdup_n_s64⚠Experimentalneon
Duplicate vector element to vector or scalar
vdup_n_u8⚠Experimentalneon
Duplicate vector element to vector or scalar
vdup_n_u16⚠Experimentalneon
Duplicate vector element to vector or scalar
vdup_n_u32⚠Experimentalneon
Duplicate vector element to vector or scalar
vdup_n_u64⚠Experimentalneon
Duplicate vector element to vector or scalar
vdupq_lane_f32⚠Experimentalneon
Set all vector lanes to the same value
vdupq_lane_p8⚠Experimentalneon
Set all vector lanes to the same value
vdupq_lane_p16⚠Experimentalneon
Set all vector lanes to the same value
vdupq_lane_s8⚠Experimentalneon
Set all vector lanes to the same value
vdupq_lane_s16⚠Experimentalneon
Set all vector lanes to the same value
vdupq_lane_s32⚠Experimentalneon
Set all vector lanes to the same value
vdupq_lane_s64⚠Experimentalneon
Set all vector lanes to the same value
vdupq_lane_u8⚠Experimentalneon
Set all vector lanes to the same value
vdupq_lane_u16⚠Experimentalneon
Set all vector lanes to the same value
vdupq_lane_u32⚠Experimentalneon
Set all vector lanes to the same value
vdupq_lane_u64⚠Experimentalneon
Set all vector lanes to the same value
vdupq_laneq_f32⚠Experimentalneon
Set all vector lanes to the same value
vdupq_laneq_p8⚠Experimentalneon
Set all vector lanes to the same value
vdupq_laneq_p16⚠Experimentalneon
Set all vector lanes to the same value
vdupq_laneq_s8⚠Experimentalneon
Set all vector lanes to the same value
vdupq_laneq_s16⚠Experimentalneon
Set all vector lanes to the same value
vdupq_laneq_s32⚠Experimentalneon
Set all vector lanes to the same value
vdupq_laneq_s64⚠Experimentalneon
Set all vector lanes to the same value
vdupq_laneq_u8⚠Experimentalneon
Set all vector lanes to the same value
vdupq_laneq_u16⚠Experimentalneon
Set all vector lanes to the same value
vdupq_laneq_u32⚠Experimentalneon
Set all vector lanes to the same value
vdupq_laneq_u64⚠Experimentalneon
Set all vector lanes to the same value
vdupq_n_f32⚠Experimentalneon
Duplicate vector element to vector or scalar
vdupq_n_p8⚠Experimentalneon
Duplicate vector element to vector or scalar
vdupq_n_p16⚠Experimentalneon
Duplicate vector element to vector or scalar
vdupq_n_s8⚠Experimentalneon
Duplicate vector element to vector or scalar
vdupq_n_s16⚠Experimentalneon
Duplicate vector element to vector or scalar
vdupq_n_s32⚠Experimentalneon
Duplicate vector element to vector or scalar
vdupq_n_s64⚠Experimentalneon
Duplicate vector element to vector or scalar
vdupq_n_u8⚠Experimentalneon
Duplicate vector element to vector or scalar
vdupq_n_u16⚠Experimentalneon
Duplicate vector element to vector or scalar
vdupq_n_u32⚠Experimentalneon
Duplicate vector element to vector or scalar
vdupq_n_u64⚠Experimentalneon
Duplicate vector element to vector or scalar
veor3q_s8⚠Experimentalneon,sha3
Three-way exclusive OR
veor3q_s16⚠Experimentalneon,sha3
Three-way exclusive OR
veor3q_s32⚠Experimentalneon,sha3
Three-way exclusive OR
veor3q_s64⚠Experimentalneon,sha3
Three-way exclusive OR
veor3q_u8⚠Experimentalneon,sha3
Three-way exclusive OR
veor3q_u16⚠Experimentalneon,sha3
Three-way exclusive OR
veor3q_u32⚠Experimentalneon,sha3
Three-way exclusive OR
veor3q_u64⚠Experimentalneon,sha3
Three-way exclusive OR
veor_s8⚠Experimentalneon
Vector bitwise exclusive or (vector)
veor_s16⚠Experimentalneon
Vector bitwise exclusive or (vector)
veor_s32⚠Experimentalneon
Vector bitwise exclusive or (vector)
veor_s64⚠Experimentalneon
Vector bitwise exclusive or (vector)
veor_u8⚠Experimentalneon
Vector bitwise exclusive or (vector)
veor_u16⚠Experimentalneon
Vector bitwise exclusive or (vector)
veor_u32⚠Experimentalneon
Vector bitwise exclusive or (vector)
veor_u64⚠Experimentalneon
Vector bitwise exclusive or (vector)
veorq_s8⚠Experimentalneon
Vector bitwise exclusive or (vector)
veorq_s16⚠Experimentalneon
Vector bitwise exclusive or (vector)
veorq_s32⚠Experimentalneon
Vector bitwise exclusive or (vector)
veorq_s64⚠Experimentalneon
Vector bitwise exclusive or (vector)
veorq_u8⚠Experimentalneon
Vector bitwise exclusive or (vector)
veorq_u16⚠Experimentalneon
Vector bitwise exclusive or (vector)
veorq_u32⚠Experimentalneon
Vector bitwise exclusive or (vector)
veorq_u64⚠Experimentalneon
Vector bitwise exclusive or (vector)
vext_f32⚠Experimentalneon
Extract vector from pair of vectors
vext_p8⚠Experimentalneon
Extract vector from pair of vectors
vext_p16⚠Experimentalneon
Extract vector from pair of vectors
vext_s8⚠Experimentalneon
Extract vector from pair of vectors
vext_s16⚠Experimentalneon
Extract vector from pair of vectors
vext_s32⚠Experimentalneon
Extract vector from pair of vectors
vext_s64⚠Experimentalneon
Extract vector from pair of vectors
vext_u8⚠Experimentalneon
Extract vector from pair of vectors
vext_u16⚠Experimentalneon
Extract vector from pair of vectors
vext_u32⚠Experimentalneon
Extract vector from pair of vectors
vext_u64⚠Experimentalneon
Extract vector from pair of vectors
vextq_f32⚠Experimentalneon
Extract vector from pair of vectors
vextq_p8⚠Experimentalneon
Extract vector from pair of vectors
vextq_p16⚠Experimentalneon
Extract vector from pair of vectors
vextq_s8⚠Experimentalneon
Extract vector from pair of vectors
vextq_s16⚠Experimentalneon
Extract vector from pair of vectors
vextq_s32⚠Experimentalneon
Extract vector from pair of vectors
vextq_s64⚠Experimentalneon
Extract vector from pair of vectors
vextq_u8⚠Experimentalneon
Extract vector from pair of vectors
vextq_u16⚠Experimentalneon
Extract vector from pair of vectors
vextq_u32⚠Experimentalneon
Extract vector from pair of vectors
vextq_u64⚠Experimentalneon
Extract vector from pair of vectors
vfma_f32⚠Experimentalneon
Floating-point fused Multiply-Add to accumulator(vector)
vfma_n_f32⚠Experimentalneon
Floating-point fused Multiply-Add to accumulator(vector)
vfmaq_f32⚠Experimentalneon
Floating-point fused Multiply-Add to accumulator(vector)
vfmaq_n_f32⚠Experimentalneon
Floating-point fused Multiply-Add to accumulator(vector)
vfms_f32⚠Experimentalneon
Floating-point fused multiply-subtract from accumulator
vfms_n_f32⚠Experimentalneon
Floating-point fused Multiply-subtract to accumulator(vector)
vfmsq_f32⚠Experimentalneon
Floating-point fused multiply-subtract from accumulator
vfmsq_n_f32⚠Experimentalneon
Floating-point fused Multiply-subtract to accumulator(vector)
vget_high_f32⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_high_p8⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_high_p16⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_high_s8⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_high_s16⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_high_s32⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_high_s64⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_high_u8⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_high_u16⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_high_u32⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_high_u64⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_lane_f32⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_lane_p8⚠Experimentalneon
Move vector element to general-purpose register
vget_lane_p16⚠Experimentalneon
Move vector element to general-purpose register
vget_lane_p64⚠Experimentalneon
Move vector element to general-purpose register
vget_lane_s8⚠Experimentalneon
Move vector element to general-purpose register
vget_lane_s16⚠Experimentalneon
Move vector element to general-purpose register
vget_lane_s32⚠Experimentalneon
Move vector element to general-purpose register
vget_lane_s64⚠Experimentalneon
Move vector element to general-purpose register
vget_lane_u8⚠Experimentalneon
Move vector element to general-purpose register
vget_lane_u16⚠Experimentalneon
Move vector element to general-purpose register
vget_lane_u32⚠Experimentalneon
Move vector element to general-purpose register
vget_lane_u64⚠Experimentalneon
Move vector element to general-purpose register
vget_low_f32⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_low_p8⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_low_p16⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_low_s8⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_low_s16⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_low_s32⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_low_s64⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_low_u8⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_low_u16⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_low_u32⚠Experimentalneon
Duplicate vector element to vector or scalar
vget_low_u64⚠Experimentalneon
Duplicate vector element to vector or scalar
vgetq_lane_f32⚠Experimentalneon
Duplicate vector element to vector or scalar
vgetq_lane_p8⚠Experimentalneon
Move vector element to general-purpose register
vgetq_lane_p16⚠Experimentalneon
Move vector element to general-purpose register
vgetq_lane_p64⚠Experimentalneon
Move vector element to general-purpose register
vgetq_lane_s8⚠Experimentalneon
Move vector element to general-purpose register
vgetq_lane_s16⚠Experimentalneon
Move vector element to general-purpose register
vgetq_lane_s32⚠Experimentalneon
Move vector element to general-purpose register
vgetq_lane_s64⚠Experimentalneon
Move vector element to general-purpose register
vgetq_lane_u8⚠Experimentalneon
Move vector element to general-purpose register
vgetq_lane_u16⚠Experimentalneon
Move vector element to general-purpose register
vgetq_lane_u32⚠Experimentalneon
Move vector element to general-purpose register
vgetq_lane_u64⚠Experimentalneon
Move vector element to general-purpose register
vhadd_s8⚠Experimentalneon
Halving add
vhadd_s16⚠Experimentalneon
Halving add
vhadd_s32⚠Experimentalneon
Halving add
vhadd_u8⚠Experimentalneon
Halving add
vhadd_u16⚠Experimentalneon
Halving add
vhadd_u32⚠Experimentalneon
Halving add
vhaddq_s8⚠Experimentalneon
Halving add
vhaddq_s16⚠Experimentalneon
Halving add
vhaddq_s32⚠Experimentalneon
Halving add
vhaddq_u8⚠Experimentalneon
Halving add
vhaddq_u16⚠Experimentalneon
Halving add
vhaddq_u32⚠Experimentalneon
Halving add
vhsub_s8⚠Experimentalneon
Signed halving subtract
vhsub_s16⚠Experimentalneon
Signed halving subtract
vhsub_s32⚠Experimentalneon
Signed halving subtract
vhsub_u8⚠Experimentalneon
Signed halving subtract
vhsub_u16⚠Experimentalneon
Signed halving subtract
vhsub_u32⚠Experimentalneon
Signed halving subtract
vhsubq_s8⚠Experimentalneon
Signed halving subtract
vhsubq_s16⚠Experimentalneon
Signed halving subtract
vhsubq_s32⚠Experimentalneon
Signed halving subtract
vhsubq_u8⚠Experimentalneon
Signed halving subtract
vhsubq_u16⚠Experimentalneon
Signed halving subtract
vhsubq_u32⚠Experimentalneon
Signed halving subtract
vld1_dup_f32⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_p8⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_p16⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_p64⚠Experimentalneon,aes
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_s8⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_s16⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_s32⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_s64⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_u8⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_u16⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_u32⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_u64⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1_f32_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_f32_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_f32_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_lane_f32⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1_lane_p8⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1_lane_p16⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1_lane_p64⚠Experimentalneon,aes
Load one single-element structure to one lane of one register.
vld1_lane_s8⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1_lane_s16⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1_lane_s32⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1_lane_s64⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1_lane_u8⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1_lane_u16⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1_lane_u32⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1_lane_u64⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1_p8_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_p8_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_p8_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_p16_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_p16_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_p16_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_p64_x2⚠Experimentalneon,aes
Load multiple single-element structures to one, two, three, or four registers
vld1_p64_x3⚠Experimentalneon,aes
Load multiple single-element structures to one, two, three, or four registers
vld1_p64_x4⚠Experimentalneon,aes
Load multiple single-element structures to one, two, three, or four registers
vld1_s8_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_s8_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_s8_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_s16_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_s16_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_s16_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_s32_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_s32_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_s32_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_s64_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_s64_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_s64_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_u8_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_u8_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_u8_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_u16_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_u16_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_u16_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_u32_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_u32_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_u32_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_u64_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_u64_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1_u64_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_dup_f32⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_p8⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_p16⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_p64⚠Experimentalneon,aes
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_s8⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_s16⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_s32⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_s64⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_u8⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_u16⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_u32⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_u64⚠Experimentalneon
Load one single-element structure and Replicate to all lanes (of one register).
vld1q_f32_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_f32_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_f32_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_lane_f32⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1q_lane_p8⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1q_lane_p16⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1q_lane_p64⚠Experimentalneon,aes
Load one single-element structure to one lane of one register.
vld1q_lane_s8⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1q_lane_s16⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1q_lane_s32⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1q_lane_s64⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1q_lane_u8⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1q_lane_u16⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1q_lane_u32⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1q_lane_u64⚠Experimentalneon
Load one single-element structure to one lane of one register.
vld1q_p8_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_p8_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_p8_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_p16_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_p16_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_p16_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_p64_x2⚠Experimentalneon,aes
Load multiple single-element structures to one, two, three, or four registers
vld1q_p64_x3⚠Experimentalneon,aes
Load multiple single-element structures to one, two, three, or four registers
vld1q_p64_x4⚠Experimentalneon,aes
Load multiple single-element structures to one, two, three, or four registers
vld1q_s8_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_s8_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_s8_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_s16_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_s16_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_s16_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_s32_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_s32_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_s32_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_s64_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_s64_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_s64_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_u8_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_u8_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_u8_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_u16_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_u16_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_u16_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_u32_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_u32_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_u32_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_u64_x2⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_u64_x3⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld1q_u64_x4⚠Experimentalneon
Load multiple single-element structures to one, two, three, or four registers
vld2_dup_p8⚠Experimentalneon
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_p16⚠Experimentalneon
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_p64⚠Experimentalneon,aes
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_u8⚠Experimentalneon
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_u16⚠Experimentalneon
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_u32⚠Experimentalneon
Load single 2-element structure and replicate to all lanes of two registers
vld2_dup_u64⚠Experimentalneon
Load single 2-element structure and replicate to all lanes of two registers
vld2_lane_p8⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2_lane_p16⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2_lane_u8⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2_lane_u16⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2_lane_u32⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2_p8⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2_p16⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2_p64⚠Experimentalneon,aes
Load multiple 2-element structures to two registers
vld2_u8⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2_u16⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2_u32⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2_u64⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2q_dup_p8⚠Experimentalneon
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_p16⚠Experimentalneon
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_u8⚠Experimentalneon
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_u16⚠Experimentalneon
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_u32⚠Experimentalneon
Load single 2-element structure and replicate to all lanes of two registers
vld2q_lane_p16⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2q_lane_u16⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2q_lane_u32⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2q_p8⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2q_p16⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2q_u8⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2q_u16⚠Experimentalneon
Load multiple 2-element structures to two registers
vld2q_u32⚠Experimentalneon
Load multiple 2-element structures to two registers
vld3_dup_p8⚠Experimentalneon
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_p16⚠Experimentalneon
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_p64⚠Experimentalneon,aes
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_u8⚠Experimentalneon
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_u16⚠Experimentalneon
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_u32⚠Experimentalneon
Load single 3-element structure and replicate to all lanes of three registers
vld3_dup_u64⚠Experimentalneon
Load single 3-element structure and replicate to all lanes of three registers
vld3_lane_p8⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3_lane_p16⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3_lane_u8⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3_lane_u16⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3_lane_u32⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3_p8⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3_p16⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3_p64⚠Experimentalneon,aes
Load multiple 3-element structures to three registers
vld3_u8⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3_u16⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3_u32⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3_u64⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3q_dup_p8⚠Experimentalneon
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_p16⚠Experimentalneon
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_u8⚠Experimentalneon
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_u16⚠Experimentalneon
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_u32⚠Experimentalneon
Load single 3-element structure and replicate to all lanes of three registers
vld3q_lane_p16⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3q_lane_u16⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3q_lane_u32⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3q_p8⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3q_p16⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3q_u8⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3q_u16⚠Experimentalneon
Load multiple 3-element structures to three registers
vld3q_u32⚠Experimentalneon
Load multiple 3-element structures to three registers
vld4_dup_p8⚠Experimentalneon
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_p16⚠Experimentalneon
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_p64⚠Experimentalneon,aes
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_u8⚠Experimentalneon
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_u16⚠Experimentalneon
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_u32⚠Experimentalneon
Load single 4-element structure and replicate to all lanes of four registers
vld4_dup_u64⚠Experimentalneon
Load single 4-element structure and replicate to all lanes of four registers
vld4_lane_p8⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4_lane_p16⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4_lane_u8⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4_lane_u16⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4_lane_u32⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4_p8⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4_p16⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4_p64⚠Experimentalneon,aes
Load multiple 4-element structures to four registers
vld4_u8⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4_u16⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4_u32⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4_u64⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4q_dup_p8⚠Experimentalneon
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_p16⚠Experimentalneon
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_u8⚠Experimentalneon
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_u16⚠Experimentalneon
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_u32⚠Experimentalneon
Load single 4-element structure and replicate to all lanes of four registers
vld4q_lane_p16⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4q_lane_u16⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4q_lane_u32⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4q_p8⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4q_p16⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4q_u8⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4q_u16⚠Experimentalneon
Load multiple 4-element structures to four registers
vld4q_u32⚠Experimentalneon
Load multiple 4-element structures to four registers
vldrq_p128⚠Experimentalneon
Load SIMD&FP register (immediate offset)
vmax_f32⚠Experimentalneon
Maximum (vector)
vmax_s8⚠Experimentalneon
Maximum (vector)
vmax_s16⚠Experimentalneon
Maximum (vector)
vmax_s32⚠Experimentalneon
Maximum (vector)
vmax_u8⚠Experimentalneon
Maximum (vector)
vmax_u16⚠Experimentalneon
Maximum (vector)
vmax_u32⚠Experimentalneon
Maximum (vector)
vmaxnm_f32⚠Experimentalneon
Floating-point Maximum Number (vector)
vmaxnmq_f32⚠Experimentalneon
Floating-point Maximum Number (vector)
vmaxq_f32⚠Experimentalneon
Maximum (vector)
vmaxq_s8⚠Experimentalneon
Maximum (vector)
vmaxq_s16⚠Experimentalneon
Maximum (vector)
vmaxq_s32⚠Experimentalneon
Maximum (vector)
vmaxq_u8⚠Experimentalneon
Maximum (vector)
vmaxq_u16⚠Experimentalneon
Maximum (vector)
vmaxq_u32⚠Experimentalneon
Maximum (vector)
vmin_f32⚠Experimentalneon
Minimum (vector)
vmin_s8⚠Experimentalneon
Minimum (vector)
vmin_s16⚠Experimentalneon
Minimum (vector)
vmin_s32⚠Experimentalneon
Minimum (vector)
vmin_u8⚠Experimentalneon
Minimum (vector)
vmin_u16⚠Experimentalneon
Minimum (vector)
vmin_u32⚠Experimentalneon
Minimum (vector)
vminnm_f32⚠Experimentalneon
Floating-point Minimum Number (vector)
vminnmq_f32⚠Experimentalneon
Floating-point Minimum Number (vector)
vminq_f32⚠Experimentalneon
Minimum (vector)
vminq_s8⚠Experimentalneon
Minimum (vector)
vminq_s16⚠Experimentalneon
Minimum (vector)
vminq_s32⚠Experimentalneon
Minimum (vector)
vminq_u8⚠Experimentalneon
Minimum (vector)
vminq_u16⚠Experimentalneon
Minimum (vector)
vminq_u32⚠Experimentalneon
Minimum (vector)
vmla_f32⚠Experimentalneon
Floating-point multiply-add to accumulator
vmla_lane_f32⚠Experimentalneon
Vector multiply accumulate with scalar
vmla_lane_s16⚠Experimentalneon
Vector multiply accumulate with scalar
vmla_lane_s32⚠Experimentalneon
Vector multiply accumulate with scalar
vmla_lane_u16⚠Experimentalneon
Vector multiply accumulate with scalar
vmla_lane_u32⚠Experimentalneon
Vector multiply accumulate with scalar
vmla_laneq_f32⚠Experimentalneon
Vector multiply accumulate with scalar
vmla_laneq_s16⚠Experimentalneon
Vector multiply accumulate with scalar
vmla_laneq_s32⚠Experimentalneon
Vector multiply accumulate with scalar
vmla_laneq_u16⚠Experimentalneon
Vector multiply accumulate with scalar
vmla_laneq_u32⚠Experimentalneon
Vector multiply accumulate with scalar
vmla_n_f32⚠Experimentalneon
Vector multiply accumulate with scalar
vmla_n_s16⚠Experimentalneon
Vector multiply accumulate with scalar
vmla_n_s32⚠Experimentalneon
Vector multiply accumulate with scalar
vmla_n_u16⚠Experimentalneon
Vector multiply accumulate with scalar
vmla_n_u32⚠Experimentalneon
Vector multiply accumulate with scalar
vmla_s8⚠Experimentalneon
Multiply-add to accumulator
vmla_s16⚠Experimentalneon
Multiply-add to accumulator
vmla_s32⚠Experimentalneon
Multiply-add to accumulator
vmla_u8⚠Experimentalneon
Multiply-add to accumulator
vmla_u16⚠Experimentalneon
Multiply-add to accumulator
vmla_u32⚠Experimentalneon
Multiply-add to accumulator
vmlal_lane_s16⚠Experimentalneon
Vector widening multiply accumulate with scalar
vmlal_lane_s32⚠Experimentalneon
Vector widening multiply accumulate with scalar
vmlal_lane_u16⚠Experimentalneon
Vector widening multiply accumulate with scalar
vmlal_lane_u32⚠Experimentalneon
Vector widening multiply accumulate with scalar
vmlal_laneq_s16⚠Experimentalneon
Vector widening multiply accumulate with scalar
vmlal_laneq_s32⚠Experimentalneon
Vector widening multiply accumulate with scalar
vmlal_laneq_u16⚠Experimentalneon
Vector widening multiply accumulate with scalar
vmlal_laneq_u32⚠Experimentalneon
Vector widening multiply accumulate with scalar
vmlal_n_s16⚠Experimentalneon
Vector widening multiply accumulate with scalar
vmlal_n_s32⚠Experimentalneon
Vector widening multiply accumulate with scalar
vmlal_n_u16⚠Experimentalneon
Vector widening multiply accumulate with scalar
vmlal_n_u32⚠Experimentalneon
Vector widening multiply accumulate with scalar
vmlal_s8⚠Experimentalneon
Signed multiply-add long
vmlal_s16⚠Experimentalneon
Signed multiply-add long
vmlal_s32⚠Experimentalneon
Signed multiply-add long
vmlal_u8⚠Experimentalneon
Unsigned multiply-add long
vmlal_u16⚠Experimentalneon
Unsigned multiply-add long
vmlal_u32⚠Experimentalneon
Unsigned multiply-add long
vmlaq_f32⚠Experimentalneon
Floating-point multiply-add to accumulator
vmlaq_lane_f32⚠Experimentalneon
Vector multiply accumulate with scalar
vmlaq_lane_s16⚠Experimentalneon
Vector multiply accumulate with scalar
vmlaq_lane_s32⚠Experimentalneon
Vector multiply accumulate with scalar
vmlaq_lane_u16⚠Experimentalneon
Vector multiply accumulate with scalar
vmlaq_lane_u32⚠Experimentalneon
Vector multiply accumulate with scalar
vmlaq_laneq_f32⚠Experimentalneon
Vector multiply accumulate with scalar
vmlaq_laneq_s16⚠Experimentalneon
Vector multiply accumulate with scalar
vmlaq_laneq_s32⚠Experimentalneon
Vector multiply accumulate with scalar
vmlaq_laneq_u16⚠Experimentalneon
Vector multiply accumulate with scalar
vmlaq_laneq_u32⚠Experimentalneon
Vector multiply accumulate with scalar
vmlaq_n_f32⚠Experimentalneon
Vector multiply accumulate with scalar
vmlaq_n_s16⚠Experimentalneon
Vector multiply accumulate with scalar
vmlaq_n_s32⚠Experimentalneon
Vector multiply accumulate with scalar
vmlaq_n_u16⚠Experimentalneon
Vector multiply accumulate with scalar
vmlaq_n_u32⚠Experimentalneon
Vector multiply accumulate with scalar
vmlaq_s8⚠Experimentalneon
Multiply-add to accumulator
vmlaq_s16⚠Experimentalneon
Multiply-add to accumulator
vmlaq_s32⚠Experimentalneon
Multiply-add to accumulator
vmlaq_u8⚠Experimentalneon
Multiply-add to accumulator
vmlaq_u16⚠Experimentalneon
Multiply-add to accumulator
vmlaq_u32⚠Experimentalneon
Multiply-add to accumulator
vmls_f32⚠Experimentalneon
Floating-point multiply-subtract from accumulator
vmls_lane_f32⚠Experimentalneon
Vector multiply subtract with scalar
vmls_lane_s16⚠Experimentalneon
Vector multiply subtract with scalar
vmls_lane_s32⚠Experimentalneon
Vector multiply subtract with scalar
vmls_lane_u16⚠Experimentalneon
Vector multiply subtract with scalar
vmls_lane_u32⚠Experimentalneon
Vector multiply subtract with scalar
vmls_laneq_f32⚠Experimentalneon
Vector multiply subtract with scalar
vmls_laneq_s16⚠Experimentalneon
Vector multiply subtract with scalar
vmls_laneq_s32⚠Experimentalneon
Vector multiply subtract with scalar
vmls_laneq_u16⚠Experimentalneon
Vector multiply subtract with scalar
vmls_laneq_u32⚠Experimentalneon
Vector multiply subtract with scalar
vmls_n_f32⚠Experimentalneon
Vector multiply subtract with scalar
vmls_n_s16⚠Experimentalneon
Vector multiply subtract with scalar
vmls_n_s32⚠Experimentalneon
Vector multiply subtract with scalar
vmls_n_u16⚠Experimentalneon
Vector multiply subtract with scalar
vmls_n_u32⚠Experimentalneon
Vector multiply subtract with scalar
vmls_s8⚠Experimentalneon
Multiply-subtract from accumulator
vmls_s16⚠Experimentalneon
Multiply-subtract from accumulator
vmls_s32⚠Experimentalneon
Multiply-subtract from accumulator
vmls_u8⚠Experimentalneon
Multiply-subtract from accumulator
vmls_u16⚠Experimentalneon
Multiply-subtract from accumulator
vmls_u32⚠Experimentalneon
Multiply-subtract from accumulator
vmlsl_lane_s16⚠Experimentalneon
Vector widening multiply subtract with scalar
vmlsl_lane_s32⚠Experimentalneon
Vector widening multiply subtract with scalar
vmlsl_lane_u16⚠Experimentalneon
Vector widening multiply subtract with scalar
vmlsl_lane_u32⚠Experimentalneon
Vector widening multiply subtract with scalar
vmlsl_laneq_s16⚠Experimentalneon
Vector widening multiply subtract with scalar
vmlsl_laneq_s32⚠Experimentalneon
Vector widening multiply subtract with scalar
vmlsl_laneq_u16⚠Experimentalneon
Vector widening multiply subtract with scalar
vmlsl_laneq_u32⚠Experimentalneon
Vector widening multiply subtract with scalar
vmlsl_n_s16⚠Experimentalneon
Vector widening multiply subtract with scalar
vmlsl_n_s32⚠Experimentalneon
Vector widening multiply subtract with scalar
vmlsl_n_u16⚠Experimentalneon
Vector widening multiply subtract with scalar
vmlsl_n_u32⚠Experimentalneon
Vector widening multiply subtract with scalar
vmlsl_s8⚠Experimentalneon
Signed multiply-subtract long
vmlsl_s16⚠Experimentalneon
Signed multiply-subtract long
vmlsl_s32⚠Experimentalneon
Signed multiply-subtract long
vmlsl_u8⚠Experimentalneon
Unsigned multiply-subtract long
vmlsl_u16⚠Experimentalneon
Unsigned multiply-subtract long
vmlsl_u32⚠Experimentalneon
Unsigned multiply-subtract long
vmlsq_f32⚠Experimentalneon
Floating-point multiply-subtract from accumulator
vmlsq_lane_f32⚠Experimentalneon
Vector multiply subtract with scalar
vmlsq_lane_s16⚠Experimentalneon
Vector multiply subtract with scalar
vmlsq_lane_s32⚠Experimentalneon
Vector multiply subtract with scalar
vmlsq_lane_u16⚠Experimentalneon
Vector multiply subtract with scalar
vmlsq_lane_u32⚠Experimentalneon
Vector multiply subtract with scalar
vmlsq_laneq_f32⚠Experimentalneon
Vector multiply subtract with scalar
vmlsq_laneq_s16⚠Experimentalneon
Vector multiply subtract with scalar
vmlsq_laneq_s32⚠Experimentalneon
Vector multiply subtract with scalar
vmlsq_laneq_u16⚠Experimentalneon
Vector multiply subtract with scalar
vmlsq_laneq_u32⚠Experimentalneon
Vector multiply subtract with scalar
vmlsq_n_f32⚠Experimentalneon
Vector multiply subtract with scalar
vmlsq_n_s16⚠Experimentalneon
Vector multiply subtract with scalar
vmlsq_n_s32⚠Experimentalneon
Vector multiply subtract with scalar
vmlsq_n_u16⚠Experimentalneon
Vector multiply subtract with scalar
vmlsq_n_u32⚠Experimentalneon
Vector multiply subtract with scalar
vmlsq_s8⚠Experimentalneon
Multiply-subtract from accumulator
vmlsq_s16⚠Experimentalneon
Multiply-subtract from accumulator
vmlsq_s32⚠Experimentalneon
Multiply-subtract from accumulator
vmlsq_u8⚠Experimentalneon
Multiply-subtract from accumulator
vmlsq_u16⚠Experimentalneon
Multiply-subtract from accumulator
vmlsq_u32⚠Experimentalneon
Multiply-subtract from accumulator
vmmlaq_s32⚠Experimentali8mm and neon
8-bit integer matrix multiply-accumulate
vmmlaq_u32⚠Experimentali8mm and neon
8-bit integer matrix multiply-accumulate
vmov_n_f32⚠Experimentalneon
Duplicate vector element to vector or scalar
vmov_n_p8⚠Experimentalneon
Duplicate vector element to vector or scalar
vmov_n_p16⚠Experimentalneon
Duplicate vector element to vector or scalar
vmov_n_s8⚠Experimentalneon
Duplicate vector element to vector or scalar
vmov_n_s16⚠Experimentalneon
Duplicate vector element to vector or scalar
vmov_n_s32⚠Experimentalneon
Duplicate vector element to vector or scalar
vmov_n_s64⚠Experimentalneon
Duplicate vector element to vector or scalar
vmov_n_u8⚠Experimentalneon
Duplicate vector element to vector or scalar
vmov_n_u16⚠Experimentalneon
Duplicate vector element to vector or scalar
vmov_n_u32⚠Experimentalneon
Duplicate vector element to vector or scalar
vmov_n_u64⚠Experimentalneon
Duplicate vector element to vector or scalar
vmovl_s8⚠Experimentalneon
Vector long move.
vmovl_s16⚠Experimentalneon
Vector long move.
vmovl_s32⚠Experimentalneon
Vector long move.
vmovl_u8⚠Experimentalneon
Vector long move.
vmovl_u16⚠Experimentalneon
Vector long move.
vmovl_u32⚠Experimentalneon
Vector long move.
vmovn_s16⚠Experimentalneon
Vector narrow integer.
vmovn_s32⚠Experimentalneon
Vector narrow integer.
vmovn_s64⚠Experimentalneon
Vector narrow integer.
vmovn_u16⚠Experimentalneon
Vector narrow integer.
vmovn_u32⚠Experimentalneon
Vector narrow integer.
vmovn_u64⚠Experimentalneon
Vector narrow integer.
vmovq_n_f32⚠Experimentalneon
Duplicate vector element to vector or scalar
vmovq_n_p8⚠Experimentalneon
Duplicate vector element to vector or scalar
vmovq_n_p16⚠Experimentalneon
Duplicate vector element to vector or scalar
vmovq_n_s8⚠Experimentalneon
Duplicate vector element to vector or scalar
vmovq_n_s16⚠Experimentalneon
Duplicate vector element to vector or scalar
vmovq_n_s32⚠Experimentalneon
Duplicate vector element to vector or scalar
vmovq_n_s64⚠Experimentalneon
Duplicate vector element to vector or scalar
vmovq_n_u8⚠Experimentalneon
Duplicate vector element to vector or scalar
vmovq_n_u16⚠Experimentalneon
Duplicate vector element to vector or scalar
vmovq_n_u32⚠Experimentalneon
Duplicate vector element to vector or scalar
vmovq_n_u64⚠Experimentalneon
Duplicate vector element to vector or scalar
vmul_f32⚠Experimentalneon
Multiply
vmul_lane_f32⚠Experimentalneon
Floating-point multiply
vmul_lane_s16⚠Experimentalneon
Multiply
vmul_lane_s32⚠Experimentalneon
Multiply
vmul_lane_u16⚠Experimentalneon
Multiply
vmul_lane_u32⚠Experimentalneon
Multiply
vmul_laneq_f32⚠Experimentalneon
Floating-point multiply
vmul_laneq_s16⚠Experimentalneon
Multiply
vmul_laneq_s32⚠Experimentalneon
Multiply
vmul_laneq_u16⚠Experimentalneon
Multiply
vmul_laneq_u32⚠Experimentalneon
Multiply
vmul_n_f32⚠Experimentalneon
Vector multiply by scalar
vmul_n_s16⚠Experimentalneon
Vector multiply by scalar
vmul_n_s32⚠Experimentalneon
Vector multiply by scalar
vmul_n_u16⚠Experimentalneon
Vector multiply by scalar
vmul_n_u32⚠Experimentalneon
Vector multiply by scalar
vmul_p8⚠Experimentalneon
Polynomial multiply
vmul_s8⚠Experimentalneon
Multiply
vmul_s16⚠Experimentalneon
Multiply
vmul_s32⚠Experimentalneon
Multiply
vmul_u8⚠Experimentalneon
Multiply
vmul_u16⚠Experimentalneon
Multiply
vmul_u32⚠Experimentalneon
Multiply
vmull_lane_s16⚠Experimentalneon
Vector long multiply by scalar
vmull_lane_s32⚠Experimentalneon
Vector long multiply by scalar
vmull_lane_u16⚠Experimentalneon
Vector long multiply by scalar
vmull_lane_u32⚠Experimentalneon
Vector long multiply by scalar
vmull_laneq_s16⚠Experimentalneon
Vector long multiply by scalar
vmull_laneq_s32⚠Experimentalneon
Vector long multiply by scalar
vmull_laneq_u16⚠Experimentalneon
Vector long multiply by scalar
vmull_laneq_u32⚠Experimentalneon
Vector long multiply by scalar
vmull_n_s16⚠Experimentalneon
Vector long multiply with scalar
vmull_n_s32⚠Experimentalneon
Vector long multiply with scalar
vmull_n_u16⚠Experimentalneon
Vector long multiply with scalar
vmull_n_u32⚠Experimentalneon
Vector long multiply with scalar
vmull_p8⚠Experimentalneon
Polynomial multiply long
vmull_s8⚠Experimentalneon
Signed multiply long
vmull_s16⚠Experimentalneon
Signed multiply long
vmull_s32⚠Experimentalneon
Signed multiply long
vmull_u8⚠Experimentalneon
Unsigned multiply long
vmull_u16⚠Experimentalneon
Unsigned multiply long
vmull_u32⚠Experimentalneon
Unsigned multiply long
vmulq_f32⚠Experimentalneon
Multiply
vmulq_lane_f32⚠Experimentalneon
Floating-point multiply
vmulq_lane_s16⚠Experimentalneon
Multiply
vmulq_lane_s32⚠Experimentalneon
Multiply
vmulq_lane_u16⚠Experimentalneon
Multiply
vmulq_lane_u32⚠Experimentalneon
Multiply
vmulq_laneq_f32⚠Experimentalneon
Floating-point multiply
vmulq_laneq_s16⚠Experimentalneon
Multiply
vmulq_laneq_s32⚠Experimentalneon
Multiply
vmulq_laneq_u16⚠Experimentalneon
Multiply
vmulq_laneq_u32⚠Experimentalneon
Multiply
vmulq_n_f32⚠Experimentalneon
Vector multiply by scalar
vmulq_n_s16⚠Experimentalneon
Vector multiply by scalar
vmulq_n_s32⚠Experimentalneon
Vector multiply by scalar
vmulq_n_u16⚠Experimentalneon
Vector multiply by scalar
vmulq_n_u32⚠Experimentalneon
Vector multiply by scalar
vmulq_p8⚠Experimentalneon
Polynomial multiply
vmulq_s8⚠Experimentalneon
Multiply
vmulq_s16⚠Experimentalneon
Multiply
vmulq_s32⚠Experimentalneon
Multiply
vmulq_u8⚠Experimentalneon
Multiply
vmulq_u16⚠Experimentalneon
Multiply
vmulq_u32⚠Experimentalneon
Multiply
vmvn_p8⚠Experimentalneon
Vector bitwise not.
vmvn_s8⚠Experimentalneon
Vector bitwise not.
vmvn_s16⚠Experimentalneon
Vector bitwise not.
vmvn_s32⚠Experimentalneon
Vector bitwise not.
vmvn_u8⚠Experimentalneon
Vector bitwise not.
vmvn_u16⚠Experimentalneon
Vector bitwise not.
vmvn_u32⚠Experimentalneon
Vector bitwise not.
vmvnq_p8⚠Experimentalneon
Vector bitwise not.
vmvnq_s8⚠Experimentalneon
Vector bitwise not.
vmvnq_s16⚠Experimentalneon
Vector bitwise not.
vmvnq_s32⚠Experimentalneon
Vector bitwise not.
vmvnq_u8⚠Experimentalneon
Vector bitwise not.
vmvnq_u16⚠Experimentalneon
Vector bitwise not.
vmvnq_u32⚠Experimentalneon
Vector bitwise not.
vneg_f32⚠Experimentalneon
Negate
vneg_s8⚠Experimentalneon
Negate
vneg_s16⚠Experimentalneon
Negate
vneg_s32⚠Experimentalneon
Negate
vnegq_f32⚠Experimentalneon
Negate
vnegq_s8⚠Experimentalneon
Negate
vnegq_s16⚠Experimentalneon
Negate
vnegq_s32⚠Experimentalneon
Negate
vorn_s8⚠Experimentalneon
Vector bitwise inclusive OR NOT
vorn_s16⚠Experimentalneon
Vector bitwise inclusive OR NOT
vorn_s32⚠Experimentalneon
Vector bitwise inclusive OR NOT
vorn_s64⚠Experimentalneon
Vector bitwise inclusive OR NOT
vorn_u8⚠Experimentalneon
Vector bitwise inclusive OR NOT
vorn_u16⚠Experimentalneon
Vector bitwise inclusive OR NOT
vorn_u32⚠Experimentalneon
Vector bitwise inclusive OR NOT
vorn_u64⚠Experimentalneon
Vector bitwise inclusive OR NOT
vornq_s8⚠Experimentalneon
Vector bitwise inclusive OR NOT
vornq_s16⚠Experimentalneon
Vector bitwise inclusive OR NOT
vornq_s32⚠Experimentalneon
Vector bitwise inclusive OR NOT
vornq_s64⚠Experimentalneon
Vector bitwise inclusive OR NOT
vornq_u8⚠Experimentalneon
Vector bitwise inclusive OR NOT
vornq_u16⚠Experimentalneon
Vector bitwise inclusive OR NOT
vornq_u32⚠Experimentalneon
Vector bitwise inclusive OR NOT
vornq_u64⚠Experimentalneon
Vector bitwise inclusive OR NOT
vorr_s8⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vorr_s16⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vorr_s32⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vorr_s64⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vorr_u8⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vorr_u16⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vorr_u32⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vorr_u64⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vorrq_s8⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vorrq_s16⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vorrq_s32⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vorrq_s64⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vorrq_u8⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vorrq_u16⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vorrq_u32⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vorrq_u64⚠Experimentalneon
Vector bitwise or (immediate, inclusive)
vpadal_s8⚠Experimentalneon
Signed Add and Accumulate Long Pairwise.
vpadal_s16⚠Experimentalneon
Signed Add and Accumulate Long Pairwise.
vpadal_s32⚠Experimentalneon
Signed Add and Accumulate Long Pairwise.
vpadal_u8⚠Experimentalneon
Unsigned Add and Accumulate Long Pairwise.
vpadal_u16⚠Experimentalneon
Unsigned Add and Accumulate Long Pairwise.
vpadal_u32⚠Experimentalneon
Unsigned Add and Accumulate Long Pairwise.
vpadalq_s8⚠Experimentalneon
Signed Add and Accumulate Long Pairwise.
vpadalq_s16⚠Experimentalneon
Signed Add and Accumulate Long Pairwise.
vpadalq_s32⚠Experimentalneon
Signed Add and Accumulate Long Pairwise.
vpadalq_u8⚠Experimentalneon
Unsigned Add and Accumulate Long Pairwise.
vpadalq_u16⚠Experimentalneon
Unsigned Add and Accumulate Long Pairwise.
vpadalq_u32⚠Experimentalneon
Unsigned Add and Accumulate Long Pairwise.
vpadd_f32⚠Experimentalneon
Floating-point add pairwise
vpadd_s8⚠Experimentalneon
Add pairwise.
vpadd_s16⚠Experimentalneon
Add pairwise.
vpadd_s32⚠Experimentalneon
Add pairwise.
vpadd_u8⚠Experimentalneon
Add pairwise.
vpadd_u16⚠Experimentalneon
Add pairwise.
vpadd_u32⚠Experimentalneon
Add pairwise.
vpaddl_s8⚠Experimentalneon
Signed Add Long Pairwise.
vpaddl_s16⚠Experimentalneon
Signed Add Long Pairwise.
vpaddl_s32⚠Experimentalneon
Signed Add Long Pairwise.
vpaddl_u8⚠Experimentalneon
Unsigned Add Long Pairwise.
vpaddl_u16⚠Experimentalneon
Unsigned Add Long Pairwise.
vpaddl_u32⚠Experimentalneon
Unsigned Add Long Pairwise.
vpaddlq_s8⚠Experimentalneon
Signed Add Long Pairwise.
vpaddlq_s16⚠Experimentalneon
Signed Add Long Pairwise.
vpaddlq_s32⚠Experimentalneon
Signed Add Long Pairwise.
vpaddlq_u8⚠Experimentalneon
Unsigned Add Long Pairwise.
vpaddlq_u16⚠Experimentalneon
Unsigned Add Long Pairwise.
vpaddlq_u32⚠Experimentalneon
Unsigned Add Long Pairwise.
vpmax_f32⚠Experimentalneon
Folding maximum of adjacent pairs
vpmax_s8⚠Experimentalneon
Folding maximum of adjacent pairs
vpmax_s16⚠Experimentalneon
Folding maximum of adjacent pairs
vpmax_s32⚠Experimentalneon
Folding maximum of adjacent pairs
vpmax_u8⚠Experimentalneon
Folding maximum of adjacent pairs
vpmax_u16⚠Experimentalneon
Folding maximum of adjacent pairs
vpmax_u32⚠Experimentalneon
Folding maximum of adjacent pairs
vpmin_f32⚠Experimentalneon
Folding minimum of adjacent pairs
vpmin_s8⚠Experimentalneon
Folding minimum of adjacent pairs
vpmin_s16⚠Experimentalneon
Folding minimum of adjacent pairs
vpmin_s32⚠Experimentalneon
Folding minimum of adjacent pairs
vpmin_u8⚠Experimentalneon
Folding minimum of adjacent pairs
vpmin_u16⚠Experimentalneon
Folding minimum of adjacent pairs
vpmin_u32⚠Experimentalneon
Folding minimum of adjacent pairs
vqabs_s8⚠Experimentalneon
Singned saturating Absolute value
vqabs_s16⚠Experimentalneon
Singned saturating Absolute value
vqabs_s32⚠Experimentalneon
Singned saturating Absolute value
vqabsq_s8⚠Experimentalneon
Singned saturating Absolute value
vqabsq_s16⚠Experimentalneon
Singned saturating Absolute value
vqabsq_s32⚠Experimentalneon
Singned saturating Absolute value
vqadd_s8⚠Experimentalneon
Saturating add
vqadd_s16⚠Experimentalneon
Saturating add
vqadd_s32⚠Experimentalneon
Saturating add
vqadd_s64⚠Experimentalneon
Saturating add
vqadd_u8⚠Experimentalneon
Saturating add
vqadd_u16⚠Experimentalneon
Saturating add
vqadd_u32⚠Experimentalneon
Saturating add
vqadd_u64⚠Experimentalneon
Saturating add
vqaddq_s8⚠Experimentalneon
Saturating add
vqaddq_s16⚠Experimentalneon
Saturating add
vqaddq_s32⚠Experimentalneon
Saturating add
vqaddq_s64⚠Experimentalneon
Saturating add
vqaddq_u8⚠Experimentalneon
Saturating add
vqaddq_u16⚠Experimentalneon
Saturating add
vqaddq_u32⚠Experimentalneon
Saturating add
vqaddq_u64⚠Experimentalneon
Saturating add
vqdmlal_lane_s16⚠Experimentalneon
Vector widening saturating doubling multiply accumulate with scalar
vqdmlal_lane_s32⚠Experimentalneon
Vector widening saturating doubling multiply accumulate with scalar
vqdmlal_n_s16⚠Experimentalneon
Vector widening saturating doubling multiply accumulate with scalar
vqdmlal_n_s32⚠Experimentalneon
Vector widening saturating doubling multiply accumulate with scalar
vqdmlal_s16⚠Experimentalneon
Signed saturating doubling multiply-add long
vqdmlal_s32⚠Experimentalneon
Signed saturating doubling multiply-add long
vqdmlsl_lane_s16⚠Experimentalneon
Vector widening saturating doubling multiply subtract with scalar
vqdmlsl_lane_s32⚠Experimentalneon
Vector widening saturating doubling multiply subtract with scalar
vqdmlsl_n_s16⚠Experimentalneon
Vector widening saturating doubling multiply subtract with scalar
vqdmlsl_n_s32⚠Experimentalneon
Vector widening saturating doubling multiply subtract with scalar
vqdmlsl_s16⚠Experimentalneon
Signed saturating doubling multiply-subtract long
vqdmlsl_s32⚠Experimentalneon
Signed saturating doubling multiply-subtract long
vqdmulh_laneq_s16⚠Experimentalneon
Vector saturating doubling multiply high by scalar
vqdmulh_laneq_s32⚠Experimentalneon
Vector saturating doubling multiply high by scalar
vqdmulh_n_s16⚠Experimentalneon
Vector saturating doubling multiply high with scalar
vqdmulh_n_s32⚠Experimentalneon
Vector saturating doubling multiply high with scalar
vqdmulh_s16⚠Experimentalneon
Signed saturating doubling multiply returning high half
vqdmulh_s32⚠Experimentalneon
Signed saturating doubling multiply returning high half
vqdmulhq_laneq_s16⚠Experimentalneon
Vector saturating doubling multiply high by scalar
vqdmulhq_laneq_s32⚠Experimentalneon
Vector saturating doubling multiply high by scalar
vqdmulhq_n_s16⚠Experimentalneon
Vector saturating doubling multiply high with scalar
vqdmulhq_n_s32⚠Experimentalneon
Vector saturating doubling multiply high with scalar
vqdmulhq_s16⚠Experimentalneon
Signed saturating doubling multiply returning high half
vqdmulhq_s32⚠Experimentalneon
Signed saturating doubling multiply returning high half
vqdmull_lane_s16⚠Experimentalneon
Vector saturating doubling long multiply by scalar
vqdmull_lane_s32⚠Experimentalneon
Vector saturating doubling long multiply by scalar
vqdmull_n_s16⚠Experimentalneon
Vector saturating doubling long multiply with scalar
vqdmull_n_s32⚠Experimentalneon
Vector saturating doubling long multiply with scalar
vqdmull_s16⚠Experimentalneon
Signed saturating doubling multiply long
vqdmull_s32⚠Experimentalneon
Signed saturating doubling multiply long
vqmovn_s16⚠Experimentalneon
Signed saturating extract narrow
vqmovn_s32⚠Experimentalneon
Signed saturating extract narrow
vqmovn_s64⚠Experimentalneon
Signed saturating extract narrow
vqmovn_u16⚠Experimentalneon
Unsigned saturating extract narrow
vqmovn_u32⚠Experimentalneon
Unsigned saturating extract narrow
vqmovn_u64⚠Experimentalneon
Unsigned saturating extract narrow
vqmovun_s16⚠Experimentalneon
Signed saturating extract unsigned narrow
vqmovun_s32⚠Experimentalneon
Signed saturating extract unsigned narrow
vqmovun_s64⚠Experimentalneon
Signed saturating extract unsigned narrow
vqneg_s8⚠Experimentalneon
Signed saturating negate
vqneg_s16⚠Experimentalneon
Signed saturating negate
vqneg_s32⚠Experimentalneon
Signed saturating negate
vqnegq_s8⚠Experimentalneon
Signed saturating negate
vqnegq_s16⚠Experimentalneon
Signed saturating negate
vqnegq_s32⚠Experimentalneon
Signed saturating negate
vqrdmulh_lane_s16⚠Experimentalneon
Vector rounding saturating doubling multiply high by scalar
vqrdmulh_lane_s32⚠Experimentalneon
Vector rounding saturating doubling multiply high by scalar
vqrdmulh_laneq_s16⚠Experimentalneon
Vector rounding saturating doubling multiply high by scalar
vqrdmulh_laneq_s32⚠Experimentalneon
Vector rounding saturating doubling multiply high by scalar
vqrdmulh_n_s16⚠Experimentalneon
Vector saturating rounding doubling multiply high with scalar
vqrdmulh_n_s32⚠Experimentalneon
Vector saturating rounding doubling multiply high with scalar
vqrdmulh_s16⚠Experimentalneon
Signed saturating rounding doubling multiply returning high half
vqrdmulh_s32⚠Experimentalneon
Signed saturating rounding doubling multiply returning high half
vqrdmulhq_lane_s16⚠Experimentalneon
Vector rounding saturating doubling multiply high by scalar
vqrdmulhq_lane_s32⚠Experimentalneon
Vector rounding saturating doubling multiply high by scalar
vqrdmulhq_laneq_s16⚠Experimentalneon
Vector rounding saturating doubling multiply high by scalar
vqrdmulhq_laneq_s32⚠Experimentalneon
Vector rounding saturating doubling multiply high by scalar
vqrdmulhq_n_s16⚠Experimentalneon
Vector saturating rounding doubling multiply high with scalar
vqrdmulhq_n_s32⚠Experimentalneon
Vector saturating rounding doubling multiply high with scalar
vqrdmulhq_s16⚠Experimentalneon
Signed saturating rounding doubling multiply returning high half
vqrdmulhq_s32⚠Experimentalneon
Signed saturating rounding doubling multiply returning high half
vqrshl_s8⚠Experimentalneon
Signed saturating rounding shift left
vqrshl_s16⚠Experimentalneon
Signed saturating rounding shift left
vqrshl_s32⚠Experimentalneon
Signed saturating rounding shift left
vqrshl_s64⚠Experimentalneon
Signed saturating rounding shift left
vqrshl_u8⚠Experimentalneon
Unsigned signed saturating rounding shift left
vqrshl_u16⚠Experimentalneon
Unsigned signed saturating rounding shift left
vqrshl_u32⚠Experimentalneon
Unsigned signed saturating rounding shift left
vqrshl_u64⚠Experimentalneon
Unsigned signed saturating rounding shift left
vqrshlq_s8⚠Experimentalneon
Signed saturating rounding shift left
vqrshlq_s16⚠Experimentalneon
Signed saturating rounding shift left
vqrshlq_s32⚠Experimentalneon
Signed saturating rounding shift left
vqrshlq_s64⚠Experimentalneon
Signed saturating rounding shift left
vqrshlq_u8⚠Experimentalneon
Unsigned signed saturating rounding shift left
vqrshlq_u16⚠Experimentalneon
Unsigned signed saturating rounding shift left
vqrshlq_u32⚠Experimentalneon
Unsigned signed saturating rounding shift left
vqrshlq_u64⚠Experimentalneon
Unsigned signed saturating rounding shift left
vqshl_n_s8⚠Experimentalneon
Signed saturating shift left
vqshl_n_s16⚠Experimentalneon
Signed saturating shift left
vqshl_n_s32⚠Experimentalneon
Signed saturating shift left
vqshl_n_s64⚠Experimentalneon
Signed saturating shift left
vqshl_n_u8⚠Experimentalneon
Unsigned saturating shift left
vqshl_n_u16⚠Experimentalneon
Unsigned saturating shift left
vqshl_n_u32⚠Experimentalneon
Unsigned saturating shift left
vqshl_n_u64⚠Experimentalneon
Unsigned saturating shift left
vqshl_s8⚠Experimentalneon
Signed saturating shift left
vqshl_s16⚠Experimentalneon
Signed saturating shift left
vqshl_s32⚠Experimentalneon
Signed saturating shift left
vqshl_s64⚠Experimentalneon
Signed saturating shift left
vqshl_u8⚠Experimentalneon
Unsigned saturating shift left
vqshl_u16⚠Experimentalneon
Unsigned saturating shift left
vqshl_u32⚠Experimentalneon
Unsigned saturating shift left
vqshl_u64⚠Experimentalneon
Unsigned saturating shift left
vqshlq_n_s8⚠Experimentalneon
Signed saturating shift left
vqshlq_n_s16⚠Experimentalneon
Signed saturating shift left
vqshlq_n_s32⚠Experimentalneon
Signed saturating shift left
vqshlq_n_s64⚠Experimentalneon
Signed saturating shift left
vqshlq_n_u8⚠Experimentalneon
Unsigned saturating shift left
vqshlq_n_u16⚠Experimentalneon
Unsigned saturating shift left
vqshlq_n_u32⚠Experimentalneon
Unsigned saturating shift left
vqshlq_n_u64⚠Experimentalneon
Unsigned saturating shift left
vqshlq_s8⚠Experimentalneon
Signed saturating shift left
vqshlq_s16⚠Experimentalneon
Signed saturating shift left
vqshlq_s32⚠Experimentalneon
Signed saturating shift left
vqshlq_s64⚠Experimentalneon
Signed saturating shift left
vqshlq_u8⚠Experimentalneon
Unsigned saturating shift left
vqshlq_u16⚠Experimentalneon
Unsigned saturating shift left
vqshlq_u32⚠Experimentalneon
Unsigned saturating shift left
vqshlq_u64⚠Experimentalneon
Unsigned saturating shift left
vqsub_s8⚠Experimentalneon
Saturating subtract
vqsub_s16⚠Experimentalneon
Saturating subtract
vqsub_s32⚠Experimentalneon
Saturating subtract
vqsub_s64⚠Experimentalneon
Saturating subtract
vqsub_u8⚠Experimentalneon
Saturating subtract
vqsub_u16⚠Experimentalneon
Saturating subtract
vqsub_u32⚠Experimentalneon
Saturating subtract
vqsub_u64⚠Experimentalneon
Saturating subtract
vqsubq_s8⚠Experimentalneon
Saturating subtract
vqsubq_s16⚠Experimentalneon
Saturating subtract
vqsubq_s32⚠Experimentalneon
Saturating subtract
vqsubq_s64⚠Experimentalneon
Saturating subtract
vqsubq_u8⚠Experimentalneon
Saturating subtract
vqsubq_u16⚠Experimentalneon
Saturating subtract
vqsubq_u32⚠Experimentalneon
Saturating subtract
vqsubq_u64⚠Experimentalneon
Saturating subtract
vraddhn_high_s16⚠Experimentalneon
Rounding Add returning High Narrow (high half).
vraddhn_high_s32⚠Experimentalneon
Rounding Add returning High Narrow (high half).
vraddhn_high_s64⚠Experimentalneon
Rounding Add returning High Narrow (high half).
vraddhn_high_u16⚠Experimentalneon
Rounding Add returning High Narrow (high half).
vraddhn_high_u32⚠Experimentalneon
Rounding Add returning High Narrow (high half).
vraddhn_high_u64⚠Experimentalneon
Rounding Add returning High Narrow (high half).
vraddhn_s16⚠Experimentalneon
Rounding Add returning High Narrow.
vraddhn_s32⚠Experimentalneon
Rounding Add returning High Narrow.
vraddhn_s64⚠Experimentalneon
Rounding Add returning High Narrow.
vraddhn_u16⚠Experimentalneon
Rounding Add returning High Narrow.
vraddhn_u32⚠Experimentalneon
Rounding Add returning High Narrow.
vraddhn_u64⚠Experimentalneon
Rounding Add returning High Narrow.
vrax1q_u64⚠Experimentalneon,sha3
Rotate and exclusive OR
vrecpe_f32⚠Experimentalneon
Reciprocal estimate.
vrecpe_u32⚠Experimentalneon
Unsigned reciprocal estimate
vrecpeq_f32⚠Experimentalneon
Reciprocal estimate.
vrecpeq_u32⚠Experimentalneon
Unsigned reciprocal estimate
vrecps_f32⚠Experimentalneon
Floating-point reciprocal step
vrecpsq_f32⚠Experimentalneon
Floating-point reciprocal step
vreinterpret_f32_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_f32_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_f32_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_f32_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_f32_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_f32_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_f32_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_f32_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_f32_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_f32_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p8_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p8_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p8_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_p8_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p8_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p8_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p8_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p8_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p8_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p8_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p8_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p16_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p16_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p16_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_p16_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p16_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p16_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p16_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p16_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p16_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p16_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p16_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_p64_p8⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_p64_p16⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_p64_s8⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_p64_s16⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_p64_s32⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_p64_u8⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_p64_u16⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_p64_u32⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_s8_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s8_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s8_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s8_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_s8_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s8_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s8_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s8_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s8_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s8_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s8_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s16_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s16_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s16_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s16_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_s16_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s16_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s16_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s16_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s16_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s16_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s16_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s32_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s32_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s32_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s32_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_s32_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s32_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s32_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s32_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s32_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s32_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s32_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s64_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s64_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s64_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s64_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s64_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s64_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s64_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s64_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s64_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_s64_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u8_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u8_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u8_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u8_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_u8_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u8_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u8_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u8_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u8_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u8_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u8_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u16_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u16_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u16_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u16_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_u16_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u16_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u16_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u16_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u16_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u16_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u16_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u32_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u32_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u32_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u32_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpret_u32_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u32_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u32_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u32_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u32_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u32_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u32_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u64_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u64_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u64_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u64_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u64_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u64_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u64_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u64_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u64_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpret_u64_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_f32_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_f32_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_f32_p128⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_f32_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_f32_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_f32_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_f32_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_f32_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_f32_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_f32_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_f32_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p8_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p8_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p8_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p8_p128⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p8_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p8_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p8_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p8_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p8_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p8_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p8_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p8_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p16_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p16_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p16_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p16_p128⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p16_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p16_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p16_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p16_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p16_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p16_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p16_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p16_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p64_p8⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p64_p16⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p64_p128⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p64_s8⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p64_s16⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p64_s32⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p64_u8⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p64_u16⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p64_u32⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p128_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_p128_p8⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p128_p16⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p128_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p128_s8⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p128_s16⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p128_s32⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p128_s64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p128_u8⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p128_u16⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p128_u32⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_p128_u64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_s8_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s8_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s8_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s8_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_s8_p128⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_s8_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s8_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s8_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s8_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s8_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s8_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s8_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s16_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s16_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s16_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s16_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_s16_p128⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_s16_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s16_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s16_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s16_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s16_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s16_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s16_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s32_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s32_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s32_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s32_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_s32_p128⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_s32_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s32_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s32_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s32_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s32_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s32_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s32_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s64_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s64_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s64_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s64_p128⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_s64_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s64_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s64_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s64_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s64_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s64_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_s64_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u8_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u8_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u8_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u8_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_u8_p128⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_u8_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u8_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u8_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u8_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u8_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u8_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u8_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u16_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u16_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u16_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u16_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_u16_p128⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_u16_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u16_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u16_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u16_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u16_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u16_u32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u16_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u32_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u32_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u32_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u32_p64⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_u32_p128⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_u32_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u32_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u32_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u32_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u32_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u32_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u32_u64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u64_f32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u64_p8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u64_p16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u64_p128⚠Experimentalneon,aes
Vector reinterpret cast operation
vreinterpretq_u64_s8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u64_s16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u64_s32⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u64_s64⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u64_u8⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u64_u16⚠Experimentalneon
Vector reinterpret cast operation
vreinterpretq_u64_u32⚠Experimentalneon
Vector reinterpret cast operation
vrev16_p8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev16_s8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev16_u8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev16q_p8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev16q_s8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev16q_u8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev32_p8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev32_p16⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev32_s8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev32_s16⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev32_u8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev32_u16⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev32q_p8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev32q_p16⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev32q_s8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev32q_s16⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev32q_u8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev32q_u16⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64_f32⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64_p8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64_p16⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64_s8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64_s16⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64_s32⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64_u8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64_u16⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64_u32⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64q_f32⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64q_p8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64q_p16⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64q_s8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64q_s16⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64q_s32⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64q_u8⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64q_u16⚠Experimentalneon
Reversing vector elements (swap endianness)
vrev64q_u32⚠Experimentalneon
Reversing vector elements (swap endianness)
vrhadd_s8⚠Experimentalneon
Rounding halving add
vrhadd_s16⚠Experimentalneon
Rounding halving add
vrhadd_s32⚠Experimentalneon
Rounding halving add
vrhadd_u8⚠Experimentalneon
Rounding halving add
vrhadd_u16⚠Experimentalneon
Rounding halving add
vrhadd_u32⚠Experimentalneon
Rounding halving add
vrhaddq_s8⚠Experimentalneon
Rounding halving add
vrhaddq_s16⚠Experimentalneon
Rounding halving add
vrhaddq_s32⚠Experimentalneon
Rounding halving add
vrhaddq_u8⚠Experimentalneon
Rounding halving add
vrhaddq_u16⚠Experimentalneon
Rounding halving add
vrhaddq_u32⚠Experimentalneon
Rounding halving add
vrnd32x_f32⚠Experimentalneon,frintts
Floating-point round to 32-bit integer, using current rounding mode
vrnd32xq_f32⚠Experimentalneon,frintts
Floating-point round to 32-bit integer, using current rounding mode
vrnd32z_f32⚠Experimentalneon,frintts
Floating-point round to 32-bit integer toward zero
vrnd32zq_f32⚠Experimentalneon,frintts
Floating-point round to 32-bit integer toward zero
vrnd64x_f32⚠Experimentalneon,frintts
Floating-point round to 64-bit integer, using current rounding mode
vrnd64xq_f32⚠Experimentalneon,frintts
Floating-point round to 64-bit integer, using current rounding mode
vrnd64z_f32⚠Experimentalneon,frintts
Floating-point round to 64-bit integer toward zero
vrnd64zq_f32⚠Experimentalneon,frintts
Floating-point round to 64-bit integer toward zero
vrndn_f32⚠Experimentalneon
Floating-point round to integral, to nearest with ties to even
vrndnq_f32⚠Experimentalneon
Floating-point round to integral, to nearest with ties to even
vrshl_s8⚠Experimentalneon
Signed rounding shift left
vrshl_s16⚠Experimentalneon
Signed rounding shift left
vrshl_s32⚠Experimentalneon
Signed rounding shift left
vrshl_s64⚠Experimentalneon
Signed rounding shift left
vrshl_u8⚠Experimentalneon
Unsigned rounding shift left
vrshl_u16⚠Experimentalneon
Unsigned rounding shift left
vrshl_u32⚠Experimentalneon
Unsigned rounding shift left
vrshl_u64⚠Experimentalneon
Unsigned rounding shift left
vrshlq_s8⚠Experimentalneon
Signed rounding shift left
vrshlq_s16⚠Experimentalneon
Signed rounding shift left
vrshlq_s32⚠Experimentalneon
Signed rounding shift left
vrshlq_s64⚠Experimentalneon
Signed rounding shift left
vrshlq_u8⚠Experimentalneon
Unsigned rounding shift left
vrshlq_u16⚠Experimentalneon
Unsigned rounding shift left
vrshlq_u32⚠Experimentalneon
Unsigned rounding shift left
vrshlq_u64⚠Experimentalneon
Unsigned rounding shift left
vrshr_n_s8⚠Experimentalneon
Signed rounding shift right
vrshr_n_s16⚠Experimentalneon
Signed rounding shift right
vrshr_n_s32⚠Experimentalneon
Signed rounding shift right
vrshr_n_s64⚠Experimentalneon
Signed rounding shift right
vrshr_n_u8⚠Experimentalneon
Unsigned rounding shift right
vrshr_n_u16⚠Experimentalneon
Unsigned rounding shift right
vrshr_n_u32⚠Experimentalneon
Unsigned rounding shift right
vrshr_n_u64⚠Experimentalneon
Unsigned rounding shift right
vrshrn_n_u16⚠Experimentalneon
Rounding shift right narrow
vrshrn_n_u32⚠Experimentalneon
Rounding shift right narrow
vrshrn_n_u64⚠Experimentalneon
Rounding shift right narrow
vrshrq_n_s8⚠Experimentalneon
Signed rounding shift right
vrshrq_n_s16⚠Experimentalneon
Signed rounding shift right
vrshrq_n_s32⚠Experimentalneon
Signed rounding shift right
vrshrq_n_s64⚠Experimentalneon
Signed rounding shift right
vrshrq_n_u8⚠Experimentalneon
Unsigned rounding shift right
vrshrq_n_u16⚠Experimentalneon
Unsigned rounding shift right
vrshrq_n_u32⚠Experimentalneon
Unsigned rounding shift right
vrshrq_n_u64⚠Experimentalneon
Unsigned rounding shift right
vrsqrte_f32⚠Experimentalneon
Reciprocal square-root estimate.
vrsqrte_u32⚠Experimentalneon
Unsigned reciprocal square root estimate
vrsqrteq_f32⚠Experimentalneon
Reciprocal square-root estimate.
vrsqrteq_u32⚠Experimentalneon
Unsigned reciprocal square root estimate
vrsqrts_f32⚠Experimentalneon
Floating-point reciprocal square root step
vrsqrtsq_f32⚠Experimentalneon
Floating-point reciprocal square root step
vrsra_n_s8⚠Experimentalneon
Signed rounding shift right and accumulate
vrsra_n_s16⚠Experimentalneon
Signed rounding shift right and accumulate
vrsra_n_s32⚠Experimentalneon
Signed rounding shift right and accumulate
vrsra_n_s64⚠Experimentalneon
Signed rounding shift right and accumulate
vrsra_n_u8⚠Experimentalneon
Unsigned rounding shift right and accumulate
vrsra_n_u16⚠Experimentalneon
Unsigned rounding shift right and accumulate
vrsra_n_u32⚠Experimentalneon
Unsigned rounding shift right and accumulate
vrsra_n_u64⚠Experimentalneon
Unsigned rounding shift right and accumulate
vrsraq_n_s8⚠Experimentalneon
Signed rounding shift right and accumulate
vrsraq_n_s16⚠Experimentalneon
Signed rounding shift right and accumulate
vrsraq_n_s32⚠Experimentalneon
Signed rounding shift right and accumulate
vrsraq_n_s64⚠Experimentalneon
Signed rounding shift right and accumulate
vrsraq_n_u8⚠Experimentalneon
Unsigned rounding shift right and accumulate
vrsraq_n_u16⚠Experimentalneon
Unsigned rounding shift right and accumulate
vrsraq_n_u32⚠Experimentalneon
Unsigned rounding shift right and accumulate
vrsraq_n_u64⚠Experimentalneon
Unsigned rounding shift right and accumulate
vrsubhn_s16⚠Experimentalneon
Rounding subtract returning high narrow
vrsubhn_s32⚠Experimentalneon
Rounding subtract returning high narrow
vrsubhn_s64⚠Experimentalneon
Rounding subtract returning high narrow
vrsubhn_u16⚠Experimentalneon
Rounding subtract returning high narrow
vrsubhn_u32⚠Experimentalneon
Rounding subtract returning high narrow
vrsubhn_u64⚠Experimentalneon
Rounding subtract returning high narrow
vset_lane_f32⚠Experimentalneon
Insert vector element from another vector element
vset_lane_p8⚠Experimentalneon
Insert vector element from another vector element
vset_lane_p16⚠Experimentalneon
Insert vector element from another vector element
vset_lane_p64⚠Experimentalneon,aes
Insert vector element from another vector element
vset_lane_s8⚠Experimentalneon
Insert vector element from another vector element
vset_lane_s16⚠Experimentalneon
Insert vector element from another vector element
vset_lane_s32⚠Experimentalneon
Insert vector element from another vector element
vset_lane_s64⚠Experimentalneon
Insert vector element from another vector element
vset_lane_u8⚠Experimentalneon
Insert vector element from another vector element
vset_lane_u16⚠Experimentalneon
Insert vector element from another vector element
vset_lane_u32⚠Experimentalneon
Insert vector element from another vector element
vset_lane_u64⚠Experimentalneon
Insert vector element from another vector element
vsetq_lane_f32⚠Experimentalneon
Insert vector element from another vector element
vsetq_lane_p8⚠Experimentalneon
Insert vector element from another vector element
vsetq_lane_p16⚠Experimentalneon
Insert vector element from another vector element
vsetq_lane_p64⚠Experimentalneon,aes
Insert vector element from another vector element
vsetq_lane_s8⚠Experimentalneon
Insert vector element from another vector element
vsetq_lane_s16⚠Experimentalneon
Insert vector element from another vector element
vsetq_lane_s32⚠Experimentalneon
Insert vector element from another vector element
vsetq_lane_s64⚠Experimentalneon
Insert vector element from another vector element
vsetq_lane_u8⚠Experimentalneon
Insert vector element from another vector element
vsetq_lane_u16⚠Experimentalneon
Insert vector element from another vector element
vsetq_lane_u32⚠Experimentalneon
Insert vector element from another vector element
vsetq_lane_u64⚠Experimentalneon
Insert vector element from another vector element
vsha1cq_u32⚠Experimentalsha2
SHA1 hash update accelerator, choose.
vsha1h_u32⚠Experimentalsha2
SHA1 fixed rotate.
vsha1mq_u32⚠Experimentalsha2
SHA1 hash update accelerator, majority.
vsha1pq_u32⚠Experimentalsha2
SHA1 hash update accelerator, parity.
vsha1su0q_u32⚠Experimentalsha2
SHA1 schedule update accelerator, first part.
vsha1su1q_u32⚠Experimentalsha2
SHA1 schedule update accelerator, second part.
vsha256h2q_u32⚠Experimentalsha2
SHA256 hash update accelerator, upper part.
vsha256hq_u32⚠Experimentalsha2
SHA256 hash update accelerator.
vsha256su0q_u32⚠Experimentalsha2
SHA256 schedule update accelerator, first part.
vsha256su1q_u32⚠Experimentalsha2
SHA256 schedule update accelerator, second part.
vsha512h2q_u64⚠Experimentalneon,sha3
SHA512 hash update part 2
vsha512hq_u64⚠Experimentalneon,sha3
SHA512 hash update part 1
vsha512su0q_u64⚠Experimentalneon,sha3
SHA512 schedule update 0
vsha512su1q_u64⚠Experimentalneon,sha3
SHA512 schedule update 1
vshl_n_s8⚠Experimentalneon
Shift left
vshl_n_s16⚠Experimentalneon
Shift left
vshl_n_s32⚠Experimentalneon
Shift left
vshl_n_s64⚠Experimentalneon
Shift left
vshl_n_u8⚠Experimentalneon
Shift left
vshl_n_u16⚠Experimentalneon
Shift left
vshl_n_u32⚠Experimentalneon
Shift left
vshl_n_u64⚠Experimentalneon
Shift left
vshl_s8⚠Experimentalneon
Signed Shift left
vshl_s16⚠Experimentalneon
Signed Shift left
vshl_s32⚠Experimentalneon
Signed Shift left
vshl_s64⚠Experimentalneon
Signed Shift left
vshl_u8⚠Experimentalneon
Unsigned Shift left
vshl_u16⚠Experimentalneon
Unsigned Shift left
vshl_u32⚠Experimentalneon
Unsigned Shift left
vshl_u64⚠Experimentalneon
Unsigned Shift left
vshll_n_s8⚠Experimentalneon
Signed shift left long
vshll_n_s16⚠Experimentalneon
Signed shift left long
vshll_n_s32⚠Experimentalneon
Signed shift left long
vshll_n_u8⚠Experimentalneon
Signed shift left long
vshll_n_u16⚠Experimentalneon
Signed shift left long
vshll_n_u32⚠Experimentalneon
Signed shift left long
vshlq_n_s8⚠Experimentalneon
Shift left
vshlq_n_s16⚠Experimentalneon
Shift left
vshlq_n_s32⚠Experimentalneon
Shift left
vshlq_n_s64⚠Experimentalneon
Shift left
vshlq_n_u8⚠Experimentalneon
Shift left
vshlq_n_u16⚠Experimentalneon
Shift left
vshlq_n_u32⚠Experimentalneon
Shift left
vshlq_n_u64⚠Experimentalneon
Shift left
vshlq_s8⚠Experimentalneon
Signed Shift left
vshlq_s16⚠Experimentalneon
Signed Shift left
vshlq_s32⚠Experimentalneon
Signed Shift left
vshlq_s64⚠Experimentalneon
Signed Shift left
vshlq_u8⚠Experimentalneon
Unsigned Shift left
vshlq_u16⚠Experimentalneon
Unsigned Shift left
vshlq_u32⚠Experimentalneon
Unsigned Shift left
vshlq_u64⚠Experimentalneon
Unsigned Shift left
vshr_n_s8⚠Experimentalneon
Shift right
vshr_n_s16⚠Experimentalneon
Shift right
vshr_n_s32⚠Experimentalneon
Shift right
vshr_n_s64⚠Experimentalneon
Shift right
vshr_n_u8⚠Experimentalneon
Shift right
vshr_n_u16⚠Experimentalneon
Shift right
vshr_n_u32⚠Experimentalneon
Shift right
vshr_n_u64⚠Experimentalneon
Shift right
vshrn_n_s16⚠Experimentalneon
Shift right narrow
vshrn_n_s32⚠Experimentalneon
Shift right narrow
vshrn_n_s64⚠Experimentalneon
Shift right narrow
vshrn_n_u16⚠Experimentalneon
Shift right narrow
vshrn_n_u32⚠Experimentalneon
Shift right narrow
vshrn_n_u64⚠Experimentalneon
Shift right narrow
vshrq_n_s8⚠Experimentalneon
Shift right
vshrq_n_s16⚠Experimentalneon
Shift right
vshrq_n_s32⚠Experimentalneon
Shift right
vshrq_n_s64⚠Experimentalneon
Shift right
vshrq_n_u8⚠Experimentalneon
Shift right
vshrq_n_u16⚠Experimentalneon
Shift right
vshrq_n_u32⚠Experimentalneon
Shift right
vshrq_n_u64⚠Experimentalneon
Shift right
vsm3partw1q_u32⚠Experimentalneon,sm4
SM3PARTW1
vsm3partw2q_u32⚠Experimentalneon,sm4
SM3PARTW2
vsm3ss1q_u32⚠Experimentalneon,sm4
SM3SS1
vsm3tt1aq_u32⚠Experimentalneon,sm4
SM3TT1A
vsm3tt1bq_u32⚠Experimentalneon,sm4
SM3TT1B
vsm3tt2aq_u32⚠Experimentalneon,sm4
SM3TT2A
vsm3tt2bq_u32⚠Experimentalneon,sm4
SM3TT2B
vsm4ekeyq_u32⚠Experimentalneon,sm4
SM4 key
vsm4eq_u32⚠Experimentalneon,sm4
SM4 encode
vsra_n_s8⚠Experimentalneon
Signed shift right and accumulate
vsra_n_s16⚠Experimentalneon
Signed shift right and accumulate
vsra_n_s32⚠Experimentalneon
Signed shift right and accumulate
vsra_n_s64⚠Experimentalneon
Signed shift right and accumulate
vsra_n_u8⚠Experimentalneon
Unsigned shift right and accumulate
vsra_n_u16⚠Experimentalneon
Unsigned shift right and accumulate
vsra_n_u32⚠Experimentalneon
Unsigned shift right and accumulate
vsra_n_u64⚠Experimentalneon
Unsigned shift right and accumulate
vsraq_n_s8⚠Experimentalneon
Signed shift right and accumulate
vsraq_n_s16⚠Experimentalneon
Signed shift right and accumulate
vsraq_n_s32⚠Experimentalneon
Signed shift right and accumulate
vsraq_n_s64⚠Experimentalneon
Signed shift right and accumulate
vsraq_n_u8⚠Experimentalneon
Unsigned shift right and accumulate
vsraq_n_u16⚠Experimentalneon
Unsigned shift right and accumulate
vsraq_n_u32⚠Experimentalneon
Unsigned shift right and accumulate
vsraq_n_u64⚠Experimentalneon
Unsigned shift right and accumulate
vst1_lane_f32⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_p8⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_p16⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_p64⚠Experimentalneon,aes
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_s8⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_s16⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_s32⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_s64⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_u8⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_u16⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_u32⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1_lane_u64⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1_p8_x2⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_p8_x3⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_p8_x4⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_p16_x2⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_p16_x3⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_p16_x4⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_p64_x2⚠Experimentalneon,aes
Store multiple single-element structures to one, two, three, or four registers
vst1_p64_x3⚠Experimentalneon,aes
Store multiple single-element structures to one, two, three, or four registers
vst1_p64_x4⚠Experimentalneon,aes
Store multiple single-element structures to one, two, three, or four registers
vst1_u8_x2⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_u8_x3⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_u8_x4⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_u16_x2⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_u16_x3⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_u16_x4⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_u32_x2⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_u32_x3⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_u32_x4⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_u64_x2⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_u64_x3⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1_u64_x4⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_lane_f32⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_p8⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_p16⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_p64⚠Experimentalneon,aes
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_s8⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_s16⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_s32⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_s64⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_u8⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_u16⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_u32⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1q_lane_u64⚠Experimentalneon
Store multiple single-element structures from one, two, three, or four registers
vst1q_p8_x2⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_p8_x3⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_p8_x4⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_p16_x2⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_p16_x3⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_p16_x4⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_p64_x2⚠Experimentalneon,aes
Store multiple single-element structures to one, two, three, or four registers
vst1q_p64_x3⚠Experimentalneon,aes
Store multiple single-element structures to one, two, three, or four registers
vst1q_p64_x4⚠Experimentalneon,aes
Store multiple single-element structures to one, two, three, or four registers
vst1q_u8_x2⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_u8_x3⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_u8_x4⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_u16_x2⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_u16_x3⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_u16_x4⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_u32_x2⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_u32_x3⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_u32_x4⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_u64_x2⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_u64_x3⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst1q_u64_x4⚠Experimentalneon
Store multiple single-element structures to one, two, three, or four registers
vst2_lane_p8⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2_lane_p16⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2_lane_u8⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2_lane_u16⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2_lane_u32⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2_p8⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2_p16⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2_p64⚠Experimentalneon,aes
Store multiple 2-element structures from two registers
vst2_u8⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2_u16⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2_u32⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2_u64⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2q_lane_p16⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2q_lane_u16⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2q_lane_u32⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2q_p8⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2q_p16⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2q_u8⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2q_u16⚠Experimentalneon
Store multiple 2-element structures from two registers
vst2q_u32⚠Experimentalneon
Store multiple 2-element structures from two registers
vst3_lane_p8⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3_lane_p16⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3_lane_u8⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3_lane_u16⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3_lane_u32⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3_p8⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3_p16⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3_p64⚠Experimentalneon,aes
Store multiple 3-element structures from three registers
vst3_u8⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3_u16⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3_u32⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3_u64⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3q_lane_p16⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3q_lane_u16⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3q_lane_u32⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3q_p8⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3q_p16⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3q_u8⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3q_u16⚠Experimentalneon
Store multiple 3-element structures from three registers
vst3q_u32⚠Experimentalneon
Store multiple 3-element structures from three registers
vst4_lane_p8⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4_lane_p16⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4_lane_u8⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4_lane_u16⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4_lane_u32⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4_p8⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4_p16⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4_p64⚠Experimentalneon,aes
Store multiple 4-element structures from four registers
vst4_u8⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4_u16⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4_u32⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4_u64⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4q_lane_p16⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4q_lane_u16⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4q_lane_u32⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4q_p8⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4q_p16⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4q_u8⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4q_u16⚠Experimentalneon
Store multiple 4-element structures from four registers
vst4q_u32⚠Experimentalneon
Store multiple 4-element structures from four registers
vstrq_p128⚠Experimentalneon
Store SIMD&FP register (immediate offset)
vsub_f32⚠Experimentalneon
Subtract
vsub_s8⚠Experimentalneon
Subtract
vsub_s16⚠Experimentalneon
Subtract
vsub_s32⚠Experimentalneon
Subtract
vsub_s64⚠Experimentalneon
Subtract
vsub_u8⚠Experimentalneon
Subtract
vsub_u16⚠Experimentalneon
Subtract
vsub_u32⚠Experimentalneon
Subtract
vsub_u64⚠Experimentalneon
Subtract
vsubhn_high_s16⚠Experimentalneon
Subtract returning high narrow
vsubhn_high_s32⚠Experimentalneon
Subtract returning high narrow
vsubhn_high_s64⚠Experimentalneon
Subtract returning high narrow
vsubhn_high_u16⚠Experimentalneon
Subtract returning high narrow
vsubhn_high_u32⚠Experimentalneon
Subtract returning high narrow
vsubhn_high_u64⚠Experimentalneon
Subtract returning high narrow
vsubhn_s16⚠Experimentalneon
Subtract returning high narrow
vsubhn_s32⚠Experimentalneon
Subtract returning high narrow
vsubhn_s64⚠Experimentalneon
Subtract returning high narrow
vsubhn_u16⚠Experimentalneon
Subtract returning high narrow
vsubhn_u32⚠Experimentalneon
Subtract returning high narrow
vsubhn_u64⚠Experimentalneon
Subtract returning high narrow
vsubl_s8⚠Experimentalneon
Signed Subtract Long
vsubl_s16⚠Experimentalneon
Signed Subtract Long
vsubl_s32⚠Experimentalneon
Signed Subtract Long
vsubl_u8⚠Experimentalneon
Unsigned Subtract Long
vsubl_u16⚠Experimentalneon
Unsigned Subtract Long
vsubl_u32⚠Experimentalneon
Unsigned Subtract Long
vsubq_f32⚠Experimentalneon
Subtract
vsubq_s8⚠Experimentalneon
Subtract
vsubq_s16⚠Experimentalneon
Subtract
vsubq_s32⚠Experimentalneon
Subtract
vsubq_s64⚠Experimentalneon
Subtract
vsubq_u8⚠Experimentalneon
Subtract
vsubq_u16⚠Experimentalneon
Subtract
vsubq_u32⚠Experimentalneon
Subtract
vsubq_u64⚠Experimentalneon
Subtract
vsubw_s8⚠Experimentalneon
Signed Subtract Wide
vsubw_s16⚠Experimentalneon
Signed Subtract Wide
vsubw_s32⚠Experimentalneon
Signed Subtract Wide
vsubw_u8⚠Experimentalneon
Unsigned Subtract Wide
vsubw_u16⚠Experimentalneon
Unsigned Subtract Wide
vsubw_u32⚠Experimentalneon
Unsigned Subtract Wide
vtrn_f32⚠Experimentalneon
Transpose elements
vtrn_p8⚠Experimentalneon
Transpose elements
vtrn_p16⚠Experimentalneon
Transpose elements
vtrn_s8⚠Experimentalneon
Transpose elements
vtrn_s16⚠Experimentalneon
Transpose elements
vtrn_s32⚠Experimentalneon
Transpose elements
vtrn_u8⚠Experimentalneon
Transpose elements
vtrn_u16⚠Experimentalneon
Transpose elements
vtrn_u32⚠Experimentalneon
Transpose elements
vtrnq_f32⚠Experimentalneon
Transpose elements
vtrnq_p8⚠Experimentalneon
Transpose elements
vtrnq_p16⚠Experimentalneon
Transpose elements
vtrnq_s8⚠Experimentalneon
Transpose elements
vtrnq_s16⚠Experimentalneon
Transpose elements
vtrnq_s32⚠Experimentalneon
Transpose elements
vtrnq_u8⚠Experimentalneon
Transpose elements
vtrnq_u16⚠Experimentalneon
Transpose elements
vtrnq_u32⚠Experimentalneon
Transpose elements
vtst_p8⚠Experimentalneon
Signed compare bitwise Test bits nonzero
vtst_p16⚠Experimentalneon
Signed compare bitwise Test bits nonzero
vtst_s8⚠Experimentalneon
Signed compare bitwise Test bits nonzero
vtst_s16⚠Experimentalneon
Signed compare bitwise Test bits nonzero
vtst_s32⚠Experimentalneon
Signed compare bitwise Test bits nonzero
vtst_u8⚠Experimentalneon
Unsigned compare bitwise Test bits nonzero
vtst_u16⚠Experimentalneon
Unsigned compare bitwise Test bits nonzero
vtst_u32⚠Experimentalneon
Unsigned compare bitwise Test bits nonzero
vtstq_p8⚠Experimentalneon
Signed compare bitwise Test bits nonzero
vtstq_p16⚠Experimentalneon
Signed compare bitwise Test bits nonzero
vtstq_s8⚠Experimentalneon
Signed compare bitwise Test bits nonzero
vtstq_s16⚠Experimentalneon
Signed compare bitwise Test bits nonzero
vtstq_s32⚠Experimentalneon
Signed compare bitwise Test bits nonzero
vtstq_u8⚠Experimentalneon
Unsigned compare bitwise Test bits nonzero
vtstq_u16⚠Experimentalneon
Unsigned compare bitwise Test bits nonzero
vtstq_u32⚠Experimentalneon
Unsigned compare bitwise Test bits nonzero
vusmmlaq_s32⚠Experimentali8mm and neon
Unsigned and signed 8-bit integer matrix multiply-accumulate
vuzp_f32⚠Experimentalneon
Unzip vectors
vuzp_p8⚠Experimentalneon
Unzip vectors
vuzp_p16⚠Experimentalneon
Unzip vectors
vuzp_s8⚠Experimentalneon
Unzip vectors
vuzp_s16⚠Experimentalneon
Unzip vectors
vuzp_s32⚠Experimentalneon
Unzip vectors
vuzp_u8⚠Experimentalneon
Unzip vectors
vuzp_u16⚠Experimentalneon
Unzip vectors
vuzp_u32⚠Experimentalneon
Unzip vectors
vuzpq_f32⚠Experimentalneon
Unzip vectors
vuzpq_p8⚠Experimentalneon
Unzip vectors
vuzpq_p16⚠Experimentalneon
Unzip vectors
vuzpq_s8⚠Experimentalneon
Unzip vectors
vuzpq_s16⚠Experimentalneon
Unzip vectors
vuzpq_s32⚠Experimentalneon
Unzip vectors
vuzpq_u8⚠Experimentalneon
Unzip vectors
vuzpq_u16⚠Experimentalneon
Unzip vectors
vuzpq_u32⚠Experimentalneon
Unzip vectors
vxarq_u64⚠Experimentalneon,sha3
Exclusive OR and rotate
vzip_f32⚠Experimentalneon
Zip vectors
vzip_p8⚠Experimentalneon
Zip vectors
vzip_p16⚠Experimentalneon
Zip vectors
vzip_s8⚠Experimentalneon
Zip vectors
vzip_s16⚠Experimentalneon
Zip vectors
vzip_s32⚠Experimentalneon
Zip vectors
vzip_u8⚠Experimentalneon
Zip vectors
vzip_u16⚠Experimentalneon
Zip vectors
vzip_u32⚠Experimentalneon
Zip vectors
vzipq_f32⚠Experimentalneon
Zip vectors
vzipq_p8⚠Experimentalneon
Zip vectors
vzipq_p16⚠Experimentalneon
Zip vectors
vzipq_s8⚠Experimentalneon
Zip vectors
vzipq_s16⚠Experimentalneon
Zip vectors
vzipq_s32⚠Experimentalneon
Zip vectors
vzipq_u8⚠Experimentalneon
Zip vectors
vzipq_u16⚠Experimentalneon
Zip vectors
vzipq_u32⚠Experimentalneon
Zip vectors
vabal_high_s8⚠neon
Signed Absolute difference and Accumulate Long
vabal_high_s16⚠neon
Signed Absolute difference and Accumulate Long
vabal_high_s32⚠neon
Signed Absolute difference and Accumulate Long
vabal_high_u8⚠neon
Unsigned Absolute difference and Accumulate Long
vabal_high_u16⚠neon
Unsigned Absolute difference and Accumulate Long
vabal_high_u32⚠neon
Unsigned Absolute difference and Accumulate Long
vabd_f64⚠neon
Absolute difference between the arguments of Floating
vabdd_f64⚠neon
Floating-point absolute difference
vabdl_high_s8⚠neon
Signed Absolute difference Long
vabdl_high_s16⚠neon
Signed Absolute difference Long
vabdl_high_s32⚠neon
Signed Absolute difference Long
vabdl_high_u8⚠neon
Unsigned Absolute difference Long
vabdl_high_u16⚠neon
Unsigned Absolute difference Long
vabdl_high_u32⚠neon
Unsigned Absolute difference Long
vabdq_f64⚠neon
Absolute difference between the arguments of Floating
vabds_f32⚠neon
Floating-point absolute difference
vabs_f64⚠neon
Floating-point absolute value
vabs_s64⚠neon
Absolute Value (wrapping).
vabsd_s64⚠neon
Absolute Value (wrapping).
vabsq_f64⚠neon
Floating-point absolute value
vabsq_s64⚠neon
Absolute Value (wrapping).
vadd_f64⚠neon
Vector add.
vadd_s64⚠neon
Vector add.
vadd_u64⚠neon
Vector add.
vaddd_s64⚠neon
Vector add.
vaddd_u64⚠neon
Vector add.
vaddlv_s8⚠neon
Signed Add Long across Vector
vaddlv_s16⚠neon
Signed Add Long across Vector
vaddlv_s32⚠neon
Signed Add Long across Vector
vaddlv_u8⚠neon
Unsigned Add Long across Vector
vaddlv_u16⚠neon
Unsigned Add Long across Vector
vaddlv_u32⚠neon
Unsigned Add Long across Vector
vaddlvq_s8⚠neon
Signed Add Long across Vector
vaddlvq_s16⚠neon
Signed Add Long across Vector
vaddlvq_s32⚠neon
Signed Add Long across Vector
vaddlvq_u8⚠neon
Unsigned Add Long across Vector
vaddlvq_u16⚠neon
Unsigned Add Long across Vector
vaddlvq_u32⚠neon
Unsigned Add Long across Vector
vaddq_f64⚠neon
Vector add.
vaddv_f32⚠neon
Floating-point add across vector
vaddv_s8⚠neon
Add across vector
vaddv_s16⚠neon
Add across vector
vaddv_s32⚠neon
Add across vector
vaddv_u8⚠neon
Add across vector
vaddv_u16⚠neon
Add across vector
vaddv_u32⚠neon
Add across vector
vaddvq_f32⚠neon
Floating-point add across vector
vaddvq_f64⚠neon
Floating-point add across vector
vaddvq_s8⚠neon
Add across vector
vaddvq_s16⚠neon
Add across vector
vaddvq_s32⚠neon
Add across vector
vaddvq_s64⚠neon
Add across vector
vaddvq_u8⚠neon
Add across vector
vaddvq_u16⚠neon
Add across vector
vaddvq_u32⚠neon
Add across vector
vaddvq_u64⚠neon
Add across vector
vbsl_f64⚠neon
Bitwise Select instructions. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.
vbsl_p64⚠neon
Bitwise Select.
vbslq_f64⚠neon
Bitwise Select. (128-bit)
vbslq_p64⚠neon
Bitwise Select. (128-bit)
vcage_f64⚠neon
Floating-point absolute compare greater than or equal
vcaged_f64⚠neon
Floating-point absolute compare greater than or equal
vcageq_f64⚠neon
Floating-point absolute compare greater than or equal
vcages_f32⚠neon
Floating-point absolute compare greater than or equal
vcagt_f64⚠neon
Floating-point absolute compare greater than
vcagtd_f64⚠neon
Floating-point absolute compare greater than
vcagtq_f64⚠neon
Floating-point absolute compare greater than
vcagts_f32⚠neon
Floating-point absolute compare greater than
vcale_f64⚠neon
Floating-point absolute compare less than or equal
vcaled_f64⚠neon
Floating-point absolute compare less than or equal
vcaleq_f64⚠neon
Floating-point absolute compare less than or equal
vcales_f32⚠neon
Floating-point absolute compare less than or equal
vcalt_f64⚠neon
Floating-point absolute compare less than
vcaltd_f64⚠neon
Floating-point absolute compare less than
vcaltq_f64⚠neon
Floating-point absolute compare less than
vcalts_f32⚠neon
Floating-point absolute compare less than
vceq_f64⚠neon
Floating-point compare equal
vceq_p64⚠neon
Compare bitwise Equal (vector)
vceq_s64⚠neon
Compare bitwise Equal (vector)
vceq_u64⚠neon
Compare bitwise Equal (vector)
vceqd_f64⚠neon
Floating-point compare equal
vceqd_s64⚠neon
Compare bitwise equal
vceqd_u64⚠neon
Compare bitwise equal
vceqq_f64⚠neon
Floating-point compare equal
vceqq_p64⚠neon
Compare bitwise Equal (vector)
vceqq_s64⚠neon
Compare bitwise Equal (vector)
vceqq_u64⚠neon
Compare bitwise Equal (vector)
vceqs_f32⚠neon
Floating-point compare equal
vceqz_f32⚠neon
Floating-point compare bitwise equal to zero
vceqz_f64⚠neon
Floating-point compare bitwise equal to zero
vceqz_p8⚠neon
Signed compare bitwise equal to zero
vceqz_p64⚠neon
Signed compare bitwise equal to zero
vceqz_s8⚠neon
Signed compare bitwise equal to zero
vceqz_s16⚠neon
Signed compare bitwise equal to zero
vceqz_s32⚠neon
Signed compare bitwise equal to zero
vceqz_s64⚠neon
Signed compare bitwise equal to zero
vceqz_u8⚠neon
Unsigned compare bitwise equal to zero
vceqz_u16⚠neon
Unsigned compare bitwise equal to zero
vceqz_u32⚠neon
Unsigned compare bitwise equal to zero
vceqz_u64⚠neon
Unsigned compare bitwise equal to zero
vceqzd_f64⚠neon
Floating-point compare bitwise equal to zero
vceqzd_s64⚠neon
Compare bitwise equal to zero
vceqzd_u64⚠neon
Compare bitwise equal to zero
vceqzq_f32⚠neon
Floating-point compare bitwise equal to zero
vceqzq_f64⚠neon
Floating-point compare bitwise equal to zero
vceqzq_p8⚠neon
Signed compare bitwise equal to zero
vceqzq_p64⚠neon
Signed compare bitwise equal to zero
vceqzq_s8⚠neon
Signed compare bitwise equal to zero
vceqzq_s16⚠neon
Signed compare bitwise equal to zero
vceqzq_s32⚠neon
Signed compare bitwise equal to zero
vceqzq_s64⚠neon
Signed compare bitwise equal to zero
vceqzq_u8⚠neon
Unsigned compare bitwise equal to zero
vceqzq_u16⚠neon
Unsigned compare bitwise equal to zero
vceqzq_u32⚠neon
Unsigned compare bitwise equal to zero
vceqzq_u64⚠neon
Unsigned compare bitwise equal to zero
vceqzs_f32⚠neon
Floating-point compare bitwise equal to zero
vcge_f64⚠neon
Floating-point compare greater than or equal
vcge_s64⚠neon
Compare signed greater than or equal
vcge_u64⚠neon
Compare unsigned greater than or equal
vcged_f64⚠neon
Floating-point compare greater than or equal
vcged_s64⚠neon
Compare greater than or equal
vcged_u64⚠neon
Compare greater than or equal
vcgeq_f64⚠neon
Floating-point compare greater than or equal
vcgeq_s64⚠neon
Compare signed greater than or equal
vcgeq_u64⚠neon
Compare unsigned greater than or equal
vcges_f32⚠neon
Floating-point compare greater than or equal
vcgez_f32⚠neon
Floating-point compare greater than or equal to zero
vcgez_f64⚠neon
Floating-point compare greater than or equal to zero
vcgez_s8⚠neon
Compare signed greater than or equal to zero
vcgez_s16⚠neon
Compare signed greater than or equal to zero
vcgez_s32⚠neon
Compare signed greater than or equal to zero
vcgez_s64⚠neon
Compare signed greater than or equal to zero
vcgezd_f64⚠neon
Floating-point compare greater than or equal to zero
vcgezd_s64⚠neon
Compare signed greater than or equal to zero
vcgezq_f32⚠neon
Floating-point compare greater than or equal to zero
vcgezq_f64⚠neon
Floating-point compare greater than or equal to zero
vcgezq_s8⚠neon
Compare signed greater than or equal to zero
vcgezq_s16⚠neon
Compare signed greater than or equal to zero
vcgezq_s32⚠neon
Compare signed greater than or equal to zero
vcgezq_s64⚠neon
Compare signed greater than or equal to zero
vcgezs_f32⚠neon
Floating-point compare greater than or equal to zero
vcgt_f64⚠neon
Floating-point compare greater than
vcgt_s64⚠neon
Compare signed greater than
vcgt_u64⚠neon
Compare unsigned highe
vcgtd_f64⚠neon
Floating-point compare greater than
vcgtd_s64⚠neon
Compare greater than
vcgtd_u64⚠neon
Compare greater than
vcgtq_f64⚠neon
Floating-point compare greater than
vcgtq_s64⚠neon
Compare signed greater than
vcgtq_u64⚠neon
Compare unsigned highe
vcgts_f32⚠neon
Floating-point compare greater than
vcgtz_f32⚠neon
Floating-point compare greater than zero
vcgtz_f64⚠neon
Floating-point compare greater than zero
vcgtz_s8⚠neon
Compare signed greater than zero
vcgtz_s16⚠neon
Compare signed greater than zero
vcgtz_s32⚠neon
Compare signed greater than zero
vcgtz_s64⚠neon
Compare signed greater than zero
vcgtzd_f64⚠neon
Floating-point compare greater than zero
vcgtzd_s64⚠neon
Compare signed greater than zero
vcgtzq_f32⚠neon
Floating-point compare greater than zero
vcgtzq_f64⚠neon
Floating-point compare greater than zero
vcgtzq_s8⚠neon
Compare signed greater than zero
vcgtzq_s16⚠neon
Compare signed greater than zero
vcgtzq_s32⚠neon
Compare signed greater than zero
vcgtzq_s64⚠neon
Compare signed greater than zero
vcgtzs_f32⚠neon
Floating-point compare greater than zero
vcle_f64⚠neon
Floating-point compare less than or equal
vcle_s64⚠neon
Compare signed less than or equal
vcle_u64⚠neon
Compare unsigned less than or equal
vcled_f64⚠neon
Floating-point compare less than or equal
vcled_s64⚠neon
Compare less than or equal
vcled_u64⚠neon
Compare less than or equal
vcleq_f64⚠neon
Floating-point compare less than or equal
vcleq_s64⚠neon
Compare signed less than or equal
vcleq_u64⚠neon
Compare unsigned less than or equal
vcles_f32⚠neon
Floating-point compare less than or equal
vclez_f32⚠neon
Floating-point compare less than or equal to zero
vclez_f64⚠neon
Floating-point compare less than or equal to zero
vclez_s8⚠neon
Compare signed less than or equal to zero
vclez_s16⚠neon
Compare signed less than or equal to zero
vclez_s32⚠neon
Compare signed less than or equal to zero
vclez_s64⚠neon
Compare signed less than or equal to zero
vclezd_f64⚠neon
Floating-point compare less than or equal to zero
vclezd_s64⚠neon
Compare less than or equal to zero
vclezq_f32⚠neon
Floating-point compare less than or equal to zero
vclezq_f64⚠neon
Floating-point compare less than or equal to zero
vclezq_s8⚠neon
Compare signed less than or equal to zero
vclezq_s16⚠neon
Compare signed less than or equal to zero
vclezq_s32⚠neon
Compare signed less than or equal to zero
vclezq_s64⚠neon
Compare signed less than or equal to zero
vclezs_f32⚠neon
Floating-point compare less than or equal to zero
vclt_f64⚠neon
Floating-point compare less than
vclt_s64⚠neon
Compare signed less than
vclt_u64⚠neon
Compare unsigned less than
vcltd_f64⚠neon
Floating-point compare less than
vcltd_s64⚠neon
Compare less than
vcltd_u64⚠neon
Compare less than
vcltq_f64⚠neon
Floating-point compare less than
vcltq_s64⚠neon
Compare signed less than
vcltq_u64⚠neon
Compare unsigned less than
vclts_f32⚠neon
Floating-point compare less than
vcltz_f32⚠neon
Floating-point compare less than zero
vcltz_f64⚠neon
Floating-point compare less than zero
vcltz_s8⚠neon
Compare signed less than zero
vcltz_s16⚠neon
Compare signed less than zero
vcltz_s32⚠neon
Compare signed less than zero
vcltz_s64⚠neon
Compare signed less than zero
vcltzd_f64⚠neon
Floating-point compare less than zero
vcltzd_s64⚠neon
Compare less than zero
vcltzq_f32⚠neon
Floating-point compare less than zero
vcltzq_f64⚠neon
Floating-point compare less than zero
vcltzq_s8⚠neon
Compare signed less than zero
vcltzq_s16⚠neon
Compare signed less than zero
vcltzq_s32⚠neon
Compare signed less than zero
vcltzq_s64⚠neon
Compare signed less than zero
vcltzs_f32⚠neon
Floating-point compare less than zero
vcombine_f32⚠neon
Vector combine
vcombine_f64⚠neon
Vector combine
vcombine_p8⚠neon
Vector combine
vcombine_p16⚠neon
Vector combine
vcombine_p64⚠neon
Vector combine
vcombine_s8⚠neon
Vector combine
vcombine_s16⚠neon
Vector combine
vcombine_s32⚠neon
Vector combine
vcombine_s64⚠neon
Vector combine
vcombine_u8⚠neon
Vector combine
vcombine_u16⚠neon
Vector combine
vcombine_u32⚠neon
Vector combine
vcombine_u64⚠neon
Vector combine
vcopy_lane_f32⚠neon
Insert vector element from another vector element
vcopy_lane_f64⚠neon
Duplicate vector element to vector or scalar
vcopy_lane_p8⚠neon
Insert vector element from another vector element
vcopy_lane_p16⚠neon
Insert vector element from another vector element
vcopy_lane_p64⚠neon
Duplicate vector element to vector or scalar
vcopy_lane_s8⚠neon
Insert vector element from another vector element
vcopy_lane_s16⚠neon
Insert vector element from another vector element
vcopy_lane_s32⚠neon
Insert vector element from another vector element
vcopy_lane_s64⚠neon
Duplicate vector element to vector or scalar
vcopy_lane_u8⚠neon
Insert vector element from another vector element
vcopy_lane_u16⚠neon
Insert vector element from another vector element
vcopy_lane_u32⚠neon
Insert vector element from another vector element
vcopy_lane_u64⚠neon
Duplicate vector element to vector or scalar
vcopy_laneq_f32⚠neon
Insert vector element from another vector element
vcopy_laneq_f64⚠neon
Duplicate vector element to vector or scalar
vcopy_laneq_p8⚠neon
Insert vector element from another vector element
vcopy_laneq_p16⚠neon
Insert vector element from another vector element
vcopy_laneq_p64⚠neon
Duplicate vector element to vector or scalar
vcopy_laneq_s8⚠neon
Insert vector element from another vector element
vcopy_laneq_s16⚠neon
Insert vector element from another vector element
vcopy_laneq_s32⚠neon
Insert vector element from another vector element
vcopy_laneq_s64⚠neon
Duplicate vector element to vector or scalar
vcopy_laneq_u8⚠neon
Insert vector element from another vector element
vcopy_laneq_u16⚠neon
Insert vector element from another vector element
vcopy_laneq_u32⚠neon
Insert vector element from another vector element
vcopy_laneq_u64⚠neon
Duplicate vector element to vector or scalar
vcopyq_lane_f32⚠neon
Insert vector element from another vector element
vcopyq_lane_f64⚠neon
Insert vector element from another vector element
vcopyq_lane_p8⚠neon
Insert vector element from another vector element
vcopyq_lane_p16⚠neon
Insert vector element from another vector element
vcopyq_lane_p64⚠neon
Insert vector element from another vector element
vcopyq_lane_s8⚠neon
Insert vector element from another vector element
vcopyq_lane_s16⚠neon
Insert vector element from another vector element
vcopyq_lane_s32⚠neon
Insert vector element from another vector element
vcopyq_lane_s64⚠neon
Insert vector element from another vector element
vcopyq_lane_u8⚠neon
Insert vector element from another vector element
vcopyq_lane_u16⚠neon
Insert vector element from another vector element
vcopyq_lane_u32⚠neon
Insert vector element from another vector element
vcopyq_lane_u64⚠neon
Insert vector element from another vector element
vcopyq_laneq_f32⚠neon
Insert vector element from another vector element
vcopyq_laneq_f64⚠neon
Insert vector element from another vector element
vcopyq_laneq_p8⚠neon
Insert vector element from another vector element
vcopyq_laneq_p16⚠neon
Insert vector element from another vector element
vcopyq_laneq_p64⚠neon
Insert vector element from another vector element
vcopyq_laneq_s8⚠neon
Insert vector element from another vector element
vcopyq_laneq_s16⚠neon
Insert vector element from another vector element
vcopyq_laneq_s32⚠neon
Insert vector element from another vector element
vcopyq_laneq_s64⚠neon
Insert vector element from another vector element
vcopyq_laneq_u8⚠neon
Insert vector element from another vector element
vcopyq_laneq_u16⚠neon
Insert vector element from another vector element
vcopyq_laneq_u32⚠neon
Insert vector element from another vector element
vcopyq_laneq_u64⚠neon
Insert vector element from another vector element
vcreate_f64⚠neon
Insert vector element from another vector element
vcvt_f32_f64⚠neon
Floating-point convert to lower precision narrow
vcvt_f64_f32⚠neon
Floating-point convert to higher precision long
vcvt_f64_s64⚠neon
Fixed-point convert to floating-point
vcvt_f64_u64⚠neon
Fixed-point convert to floating-point
vcvt_high_f32_f64⚠neon
Floating-point convert to lower precision narrow
vcvt_high_f64_f32⚠neon
Floating-point convert to higher precision long
vcvt_n_f64_s64⚠neon
Fixed-point convert to floating-point
vcvt_n_f64_u64⚠neon
Fixed-point convert to floating-point
vcvt_n_s64_f64⚠neon
Floating-point convert to fixed-point, rounding toward zero
vcvt_n_u64_f64⚠neon
Floating-point convert to fixed-point, rounding toward zero
vcvt_s64_f64⚠neon
Floating-point convert to signed fixed-point, rounding toward zero
vcvt_u64_f64⚠neon
Floating-point convert to unsigned fixed-point, rounding toward zero
vcvta_s32_f32⚠neon
Floating-point convert to signed integer, rounding to nearest with ties to away
vcvta_s64_f64⚠neon
Floating-point convert to signed integer, rounding to nearest with ties to away
vcvta_u32_f32⚠neon
Floating-point convert to unsigned integer, rounding to nearest with ties to away
vcvta_u64_f64⚠neon
Floating-point convert to unsigned integer, rounding to nearest with ties to away
vcvtad_s64_f64⚠neon
Floating-point convert to integer, rounding to nearest with ties to away
vcvtad_u64_f64⚠neon
Floating-point convert to integer, rounding to nearest with ties to away
vcvtaq_s32_f32⚠neon
Floating-point convert to signed integer, rounding to nearest with ties to away
vcvtaq_s64_f64⚠neon
Floating-point convert to signed integer, rounding to nearest with ties to away
vcvtaq_u32_f32⚠neon
Floating-point convert to unsigned integer, rounding to nearest with ties to away
vcvtaq_u64_f64⚠neon
Floating-point convert to unsigned integer, rounding to nearest with ties to away
vcvtas_s32_f32⚠neon
Floating-point convert to integer, rounding to nearest with ties to away
vcvtas_u32_f32⚠neon
Floating-point convert to integer, rounding to nearest with ties to away
vcvtd_f64_s64⚠neon
Fixed-point convert to floating-point
vcvtd_f64_u64⚠neon
Fixed-point convert to floating-point
vcvtd_n_f64_s64⚠neon
Fixed-point convert to floating-point
vcvtd_n_f64_u64⚠neon
Fixed-point convert to floating-point
vcvtd_n_s64_f64⚠neon
Floating-point convert to fixed-point, rounding toward zero
vcvtd_n_u64_f64⚠neon
Floating-point convert to fixed-point, rounding toward zero
vcvtd_s64_f64⚠neon
Fixed-point convert to floating-point
vcvtd_u64_f64⚠neon
Fixed-point convert to floating-point
vcvtm_s32_f32⚠neon
Floating-point convert to signed integer, rounding toward minus infinity
vcvtm_s64_f64⚠neon
Floating-point convert to signed integer, rounding toward minus infinity
vcvtm_u32_f32⚠neon
Floating-point convert to unsigned integer, rounding toward minus infinity
vcvtm_u64_f64⚠neon
Floating-point convert to unsigned integer, rounding toward minus infinity
vcvtmd_s64_f64⚠neon
Floating-point convert to signed integer, rounding toward minus infinity
vcvtmd_u64_f64⚠neon
Floating-point convert to unsigned integer, rounding toward minus infinity
vcvtmq_s32_f32⚠neon
Floating-point convert to signed integer, rounding toward minus infinity
vcvtmq_s64_f64⚠neon
Floating-point convert to signed integer, rounding toward minus infinity
vcvtmq_u32_f32⚠neon
Floating-point convert to unsigned integer, rounding toward minus infinity
vcvtmq_u64_f64⚠neon
Floating-point convert to unsigned integer, rounding toward minus infinity
vcvtms_s32_f32⚠neon
Floating-point convert to signed integer, rounding toward minus infinity
vcvtms_u32_f32⚠neon
Floating-point convert to unsigned integer, rounding toward minus infinity
vcvtn_s32_f32⚠neon
Floating-point convert to signed integer, rounding to nearest with ties to even
vcvtn_s64_f64⚠neon
Floating-point convert to signed integer, rounding to nearest with ties to even
vcvtn_u32_f32⚠neon
Floating-point convert to unsigned integer, rounding to nearest with ties to even
vcvtn_u64_f64⚠neon
Floating-point convert to unsigned integer, rounding to nearest with ties to even
vcvtnd_s64_f64⚠neon
Floating-point convert to signed integer, rounding to nearest with ties to even
vcvtnd_u64_f64⚠neon
Floating-point convert to unsigned integer, rounding to nearest with ties to even
vcvtnq_s32_f32⚠neon
Floating-point convert to signed integer, rounding to nearest with ties to even
vcvtnq_s64_f64⚠neon
Floating-point convert to signed integer, rounding to nearest with ties to even
vcvtnq_u32_f32⚠neon
Floating-point convert to unsigned integer, rounding to nearest with ties to even
vcvtnq_u64_f64⚠neon
Floating-point convert to unsigned integer, rounding to nearest with ties to even
vcvtns_s32_f32⚠neon
Floating-point convert to signed integer, rounding to nearest with ties to even
vcvtns_u32_f32⚠neon
Floating-point convert to unsigned integer, rounding to nearest with ties to even
vcvtp_s32_f32⚠neon
Floating-point convert to signed integer, rounding toward plus infinity
vcvtp_s64_f64⚠neon
Floating-point convert to signed integer, rounding toward plus infinity
vcvtp_u32_f32⚠neon
Floating-point convert to unsigned integer, rounding toward plus infinity
vcvtp_u64_f64⚠neon
Floating-point convert to unsigned integer, rounding toward plus infinity
vcvtpd_s64_f64⚠neon
Floating-point convert to signed integer, rounding toward plus infinity
vcvtpd_u64_f64⚠neon
Floating-point convert to unsigned integer, rounding toward plus infinity
vcvtpq_s32_f32⚠neon
Floating-point convert to signed integer, rounding toward plus infinity
vcvtpq_s64_f64⚠neon
Floating-point convert to signed integer, rounding toward plus infinity
vcvtpq_u32_f32⚠neon
Floating-point convert to unsigned integer, rounding toward plus infinity
vcvtpq_u64_f64⚠neon
Floating-point convert to unsigned integer, rounding toward plus infinity
vcvtps_s32_f32⚠neon
Floating-point convert to signed integer, rounding toward plus infinity
vcvtps_u32_f32⚠neon
Floating-point convert to unsigned integer, rounding toward plus infinity
vcvtq_f64_s64⚠neon
Fixed-point convert to floating-point
vcvtq_f64_u64⚠neon
Fixed-point convert to floating-point
vcvtq_n_f64_s64⚠neon
Fixed-point convert to floating-point
vcvtq_n_f64_u64⚠neon
Fixed-point convert to floating-point
vcvtq_n_s64_f64⚠neon
Floating-point convert to fixed-point, rounding toward zero
vcvtq_n_u64_f64⚠neon
Floating-point convert to fixed-point, rounding toward zero
vcvtq_s64_f64⚠neon
Floating-point convert to signed fixed-point, rounding toward zero
vcvtq_u64_f64⚠neon
Floating-point convert to unsigned fixed-point, rounding toward zero
vcvts_f32_s32⚠neon
Fixed-point convert to floating-point
vcvts_f32_u32⚠neon
Fixed-point convert to floating-point
vcvts_n_f32_s32⚠neon
Fixed-point convert to floating-point
vcvts_n_f32_u32⚠neon
Fixed-point convert to floating-point
vcvts_n_s32_f32⚠neon
Floating-point convert to fixed-point, rounding toward zero
vcvts_n_u32_f32⚠neon
Floating-point convert to fixed-point, rounding toward zero
vcvts_s32_f32⚠neon
Fixed-point convert to floating-point
vcvts_u32_f32⚠neon
Fixed-point convert to floating-point
vcvtx_f32_f64⚠neon
Floating-point convert to lower precision narrow, rounding to odd
vcvtx_high_f32_f64⚠neon
Floating-point convert to lower precision narrow, rounding to odd
vcvtxd_f32_f64⚠neon
Floating-point convert to lower precision narrow, rounding to odd
vdiv_f32⚠neon
Divide
vdiv_f64⚠neon
Divide
vdivq_f32⚠neon
Divide
vdivq_f64⚠neon
Divide
vdup_lane_f64⚠neon
Set all vector lanes to the same value
vdup_lane_p64⚠neon
Set all vector lanes to the same value
vdup_laneq_f64⚠neon
Set all vector lanes to the same value
vdup_laneq_p64⚠neon
Set all vector lanes to the same value
vdup_n_f64⚠neon
Duplicate vector element to vector or scalar
vdup_n_p64⚠neon
Duplicate vector element to vector or scalar
vdupb_lane_p8⚠neon
Set all vector lanes to the same value
vdupb_lane_s8⚠neon
Set all vector lanes to the same value
vdupb_lane_u8⚠neon
Set all vector lanes to the same value
vdupb_laneq_p8⚠neon
Set all vector lanes to the same value
vdupb_laneq_s8⚠neon
Set all vector lanes to the same value
vdupb_laneq_u8⚠neon
Set all vector lanes to the same value
vdupd_lane_f64⚠neon
Set all vector lanes to the same value
vdupd_lane_s64⚠neon
Set all vector lanes to the same value
vdupd_lane_u64⚠neon
Set all vector lanes to the same value
vdupd_laneq_f64⚠neon
Set all vector lanes to the same value
vdupd_laneq_s64⚠neon
Set all vector lanes to the same value
vdupd_laneq_u64⚠neon
Set all vector lanes to the same value
vduph_lane_p16⚠neon
Set all vector lanes to the same value
vduph_lane_s16⚠neon
Set all vector lanes to the same value
vduph_lane_u16⚠neon
Set all vector lanes to the same value
vduph_laneq_p16⚠neon
Set all vector lanes to the same value
vduph_laneq_s16⚠neon
Set all vector lanes to the same value
vduph_laneq_u16⚠neon
Set all vector lanes to the same value
vdupq_lane_f64⚠neon
Set all vector lanes to the same value
vdupq_lane_p64⚠neon
Set all vector lanes to the same value
vdupq_laneq_f64⚠neon
Set all vector lanes to the same value
vdupq_laneq_p64⚠neon
Set all vector lanes to the same value
vdupq_n_f64⚠neon
Duplicate vector element to vector or scalar
vdupq_n_p64⚠neon
Duplicate vector element to vector or scalar
vdups_lane_f32⚠neon
Set all vector lanes to the same value
vdups_lane_s32⚠neon
Set all vector lanes to the same value
vdups_lane_u32⚠neon
Set all vector lanes to the same value
vdups_laneq_f32⚠neon
Set all vector lanes to the same value
vdups_laneq_s32⚠neon
Set all vector lanes to the same value
vdups_laneq_u32⚠neon
Set all vector lanes to the same value
vext_f64⚠neon
Extract vector from pair of vectors
vext_p64⚠neon
Extract vector from pair of vectors
vextq_f64⚠neon
Extract vector from pair of vectors
vextq_p64⚠neon
Extract vector from pair of vectors
vfma_f64⚠neon
Floating-point fused Multiply-Add to accumulator(vector)
vfma_lane_f32⚠neon
Floating-point fused multiply-add to accumulator
vfma_lane_f64⚠neon
Floating-point fused multiply-add to accumulator
vfma_laneq_f32⚠neon
Floating-point fused multiply-add to accumulator
vfma_laneq_f64⚠neon
Floating-point fused multiply-add to accumulator
vfma_n_f64⚠neon
Floating-point fused Multiply-Add to accumulator(vector)
vfmad_lane_f64⚠neon
Floating-point fused multiply-add to accumulator
vfmad_laneq_f64⚠neon
Floating-point fused multiply-add to accumulator
vfmaq_f64⚠neon
Floating-point fused Multiply-Add to accumulator(vector)
vfmaq_lane_f32⚠neon
Floating-point fused multiply-add to accumulator
vfmaq_lane_f64⚠neon
Floating-point fused multiply-add to accumulator
vfmaq_laneq_f32⚠neon
Floating-point fused multiply-add to accumulator
vfmaq_laneq_f64⚠neon
Floating-point fused multiply-add to accumulator
vfmaq_n_f64⚠neon
Floating-point fused Multiply-Add to accumulator(vector)
vfmas_lane_f32⚠neon
Floating-point fused multiply-add to accumulator
vfmas_laneq_f32⚠neon
Floating-point fused multiply-add to accumulator
vfms_f64⚠neon
Floating-point fused multiply-subtract from accumulator
vfms_lane_f32⚠neon
Floating-point fused multiply-subtract to accumulator
vfms_lane_f64⚠neon
Floating-point fused multiply-subtract to accumulator
vfms_laneq_f32⚠neon
Floating-point fused multiply-subtract to accumulator
vfms_laneq_f64⚠neon
Floating-point fused multiply-subtract to accumulator
vfms_n_f64⚠neon
Floating-point fused Multiply-subtract to accumulator(vector)
vfmsd_lane_f64⚠neon
Floating-point fused multiply-subtract to accumulator
vfmsd_laneq_f64⚠neon
Floating-point fused multiply-subtract to accumulator
vfmsq_f64⚠neon
Floating-point fused multiply-subtract from accumulator
vfmsq_lane_f32⚠neon
Floating-point fused multiply-subtract to accumulator
vfmsq_lane_f64⚠neon
Floating-point fused multiply-subtract to accumulator
vfmsq_laneq_f32⚠neon
Floating-point fused multiply-subtract to accumulator
vfmsq_laneq_f64⚠neon
Floating-point fused multiply-subtract to accumulator
vfmsq_n_f64⚠neon
Floating-point fused Multiply-subtract to accumulator(vector)
vfmss_lane_f32⚠neon
Floating-point fused multiply-subtract to accumulator
vfmss_laneq_f32⚠neon
Floating-point fused multiply-subtract to accumulator
vget_high_f64⚠neon
Duplicate vector element to vector or scalar
vget_high_p64⚠neon
Duplicate vector element to vector or scalar
vget_lane_f64⚠neon
Duplicate vector element to vector or scalar
vget_low_f64⚠neon
Duplicate vector element to vector or scalar
vget_low_p64⚠neon
Duplicate vector element to vector or scalar
vgetq_lane_f64⚠neon
Duplicate vector element to vector or scalar
vld1_dup_f64⚠neon
Load multiple single-element structures to one, two, three, or four registers
vld1_f32⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_f64⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_f64_x2⚠neon
Load multiple single-element structures to one, two, three, or four registers
vld1_f64_x3⚠neon
Load multiple single-element structures to one, two, three, or four registers
vld1_f64_x4⚠neon
Load multiple single-element structures to one, two, three, or four registers
vld1_lane_f64⚠neon
Load one single-element structure to one lane of one register.
vld1_p8⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_p16⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_p64⚠neon,aes
Load multiple single-element structures to one, two, three, or four registers.
vld1_s8⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_s16⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_s32⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_s64⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_u8⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_u16⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_u32⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1_u64⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_dup_f64⚠neon
Load multiple single-element structures to one, two, three, or four registers
vld1q_f32⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_f64⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_f64_x2⚠neon
Load multiple single-element structures to one, two, three, or four registers
vld1q_f64_x3⚠neon
Load multiple single-element structures to one, two, three, or four registers
vld1q_f64_x4⚠neon
Load multiple single-element structures to one, two, three, or four registers
vld1q_lane_f64⚠neon
Load one single-element structure to one lane of one register.
vld1q_p8⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_p16⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_p64⚠neon,aes
Load multiple single-element structures to one, two, three, or four registers.
vld1q_s8⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_s16⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_s32⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_s64⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_u8⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_u16⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_u32⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld1q_u64⚠neon
Load multiple single-element structures to one, two, three, or four registers.
vld2_dup_f64⚠neon
Load single 2-element structure and replicate to all lanes of two registers
vld2_f64⚠neon
Load multiple 2-element structures to two registers
vld2_lane_f64⚠neon
Load multiple 2-element structures to two registers
vld2_lane_p64⚠neon,aes
Load multiple 2-element structures to two registers
vld2_lane_s64⚠neon
Load multiple 2-element structures to two registers
vld2_lane_u64⚠neon
Load multiple 2-element structures to two registers
vld2q_dup_f64⚠neon
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_p64⚠neon,aes
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_s64⚠neon
Load single 2-element structure and replicate to all lanes of two registers
vld2q_dup_u64⚠neon
Load single 2-element structure and replicate to all lanes of two registers
vld2q_f64⚠neon
Load multiple 2-element structures to two registers
vld2q_lane_f64⚠neon
Load multiple 2-element structures to two registers
vld2q_lane_p8⚠neon
Load multiple 2-element structures to two registers
vld2q_lane_p64⚠neon,aes
Load multiple 2-element structures to two registers
vld2q_lane_s8⚠neon
Load multiple 2-element structures to two registers
vld2q_lane_s64⚠neon
Load multiple 2-element structures to two registers
vld2q_lane_u8⚠neon
Load multiple 2-element structures to two registers
vld2q_lane_u64⚠neon
Load multiple 2-element structures to two registers
vld2q_p64⚠neon,aes
Load multiple 2-element structures to two registers
vld2q_s64⚠neon
Load multiple 2-element structures to two registers
vld2q_u64⚠neon
Load multiple 2-element structures to two registers
vld3_dup_f64⚠neon
Load single 3-element structure and replicate to all lanes of three registers
vld3_f64⚠neon
Load multiple 3-element structures to three registers
vld3_lane_f64⚠neon
Load multiple 3-element structures to three registers
vld3_lane_p64⚠neon,aes
Load multiple 3-element structures to three registers
vld3_lane_s64⚠neon
Load multiple 3-element structures to two registers
vld3_lane_u64⚠neon
Load multiple 3-element structures to three registers
vld3q_dup_f64⚠neon
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_p64⚠neon,aes
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_s64⚠neon
Load single 3-element structure and replicate to all lanes of three registers
vld3q_dup_u64⚠neon
Load single 3-element structure and replicate to all lanes of three registers
vld3q_f64⚠neon
Load multiple 3-element structures to three registers
vld3q_lane_f64⚠neon
Load multiple 3-element structures to three registers
vld3q_lane_p8⚠neon
Load multiple 3-element structures to three registers
vld3q_lane_p64⚠neon,aes
Load multiple 3-element structures to three registers
vld3q_lane_s8⚠neon
Load multiple 3-element structures to two registers
vld3q_lane_s64⚠neon
Load multiple 3-element structures to two registers
vld3q_lane_u8⚠neon
Load multiple 3-element structures to three registers
vld3q_lane_u64⚠neon
Load multiple 3-element structures to three registers
vld3q_p64⚠neon,aes
Load multiple 3-element structures to three registers
vld3q_s64⚠neon
Load multiple 3-element structures to three registers
vld3q_u64⚠neon
Load multiple 3-element structures to three registers
vld4_dup_f64⚠neon
Load single 4-element structure and replicate to all lanes of four registers
vld4_f64⚠neon
Load multiple 4-element structures to four registers
vld4_lane_f64⚠neon
Load multiple 4-element structures to four registers
vld4_lane_p64⚠neon,aes
Load multiple 4-element structures to four registers
vld4_lane_s64⚠neon
Load multiple 4-element structures to four registers
vld4_lane_u64⚠neon
Load multiple 4-element structures to four registers
vld4q_dup_f64⚠neon
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_p64⚠neon,aes
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_s64⚠neon
Load single 4-element structure and replicate to all lanes of four registers
vld4q_dup_u64⚠neon
Load single 4-element structure and replicate to all lanes of four registers
vld4q_f64⚠neon
Load multiple 4-element structures to four registers
vld4q_lane_f64⚠neon
Load multiple 4-element structures to four registers
vld4q_lane_p8⚠neon
Load multiple 4-element structures to four registers
vld4q_lane_p64⚠neon,aes
Load multiple 4-element structures to four registers
vld4q_lane_s8⚠neon
Load multiple 4-element structures to four registers
vld4q_lane_s64⚠neon
Load multiple 4-element structures to four registers
vld4q_lane_u8⚠neon
Load multiple 4-element structures to four registers
vld4q_lane_u64⚠neon
Load multiple 4-element structures to four registers
vld4q_p64⚠neon,aes
Load multiple 4-element structures to four registers
vld4q_s64⚠neon
Load multiple 4-element structures to four registers
vld4q_u64⚠neon
Load multiple 4-element structures to four registers
vmax_f64⚠neon
Maximum (vector)
vmaxnm_f64⚠neon
Floating-point Maximum Number (vector)
vmaxnmq_f64⚠neon
Floating-point Maximum Number (vector)
vmaxnmv_f32⚠neon
Floating-point maximum number across vector
vmaxnmvq_f32⚠neon
Floating-point maximum number across vector
vmaxnmvq_f64⚠neon
Floating-point maximum number across vector
vmaxq_f64⚠neon
Maximum (vector)
vmaxv_f32⚠neon
Horizontal vector max.
vmaxv_s8⚠neon
Horizontal vector max.
vmaxv_s16⚠neon
Horizontal vector max.
vmaxv_s32⚠neon
Horizontal vector max.
vmaxv_u8⚠neon
Horizontal vector max.
vmaxv_u16⚠neon
Horizontal vector max.
vmaxv_u32⚠neon
Horizontal vector max.
vmaxvq_f32⚠neon
Horizontal vector max.
vmaxvq_f64⚠neon
Horizontal vector max.
vmaxvq_s8⚠neon
Horizontal vector max.
vmaxvq_s16⚠neon
Horizontal vector max.
vmaxvq_s32⚠neon
Horizontal vector max.
vmaxvq_u8⚠neon
Horizontal vector max.
vmaxvq_u16⚠neon
Horizontal vector max.
vmaxvq_u32⚠neon
Horizontal vector max.
vmin_f64⚠neon
Minimum (vector)
vminnm_f64⚠neon
Floating-point Minimum Number (vector)
vminnmq_f64⚠neon
Floating-point Minimum Number (vector)
vminnmv_f32⚠neon
Floating-point minimum number across vector
vminnmvq_f32⚠neon
Floating-point minimum number across vector
vminnmvq_f64⚠neon
Floating-point minimum number across vector
vminq_f64⚠neon
Minimum (vector)
vminv_f32⚠neon
Horizontal vector min.
vminv_s8⚠neon
Horizontal vector min.
vminv_s16⚠neon
Horizontal vector min.
vminv_s32⚠neon
Horizontal vector min.
vminv_u8⚠neon
Horizontal vector min.
vminv_u16⚠neon
Horizontal vector min.
vminv_u32⚠neon
Horizontal vector min.
vminvq_f32⚠neon
Horizontal vector min.
vminvq_f64⚠neon
Horizontal vector min.
vminvq_s8⚠neon
Horizontal vector min.
vminvq_s16⚠neon
Horizontal vector min.
vminvq_s32⚠neon
Horizontal vector min.
vminvq_u8⚠neon
Horizontal vector min.
vminvq_u16⚠neon
Horizontal vector min.
vminvq_u32⚠neon
Horizontal vector min.
vmla_f64⚠neon
Floating-point multiply-add to accumulator
vmlal_high_lane_s16⚠neon
Multiply-add long
vmlal_high_lane_s32⚠neon
Multiply-add long
vmlal_high_lane_u16⚠neon
Multiply-add long
vmlal_high_lane_u32⚠neon
Multiply-add long
vmlal_high_laneq_s16⚠neon
Multiply-add long
vmlal_high_laneq_s32⚠neon
Multiply-add long
vmlal_high_laneq_u16⚠neon
Multiply-add long
vmlal_high_laneq_u32⚠neon
Multiply-add long
vmlal_high_n_s16⚠neon
Multiply-add long
vmlal_high_n_s32⚠neon
Multiply-add long
vmlal_high_n_u16⚠neon
Multiply-add long
vmlal_high_n_u32⚠neon
Multiply-add long
vmlal_high_s8⚠neon
Signed multiply-add long
vmlal_high_s16⚠neon
Signed multiply-add long
vmlal_high_s32⚠neon
Signed multiply-add long
vmlal_high_u8⚠neon
Unsigned multiply-add long
vmlal_high_u16⚠neon
Unsigned multiply-add long
vmlal_high_u32⚠neon
Unsigned multiply-add long
vmlaq_f64⚠neon
Floating-point multiply-add to accumulator
vmls_f64⚠neon
Floating-point multiply-subtract from accumulator
vmlsl_high_lane_s16⚠neon
Multiply-subtract long
vmlsl_high_lane_s32⚠neon
Multiply-subtract long
vmlsl_high_lane_u16⚠neon
Multiply-subtract long
vmlsl_high_lane_u32⚠neon
Multiply-subtract long
vmlsl_high_laneq_s16⚠neon
Multiply-subtract long
vmlsl_high_laneq_s32⚠neon
Multiply-subtract long
vmlsl_high_laneq_u16⚠neon
Multiply-subtract long
vmlsl_high_laneq_u32⚠neon
Multiply-subtract long
vmlsl_high_n_s16⚠neon
Multiply-subtract long
vmlsl_high_n_s32⚠neon
Multiply-subtract long
vmlsl_high_n_u16⚠neon
Multiply-subtract long
vmlsl_high_n_u32⚠neon
Multiply-subtract long
vmlsl_high_s8⚠neon
Signed multiply-subtract long
vmlsl_high_s16⚠neon
Signed multiply-subtract long
vmlsl_high_s32⚠neon
Signed multiply-subtract long
vmlsl_high_u8⚠neon
Unsigned multiply-subtract long
vmlsl_high_u16⚠neon
Unsigned multiply-subtract long
vmlsl_high_u32⚠neon
Unsigned multiply-subtract long
vmlsq_f64⚠neon
Floating-point multiply-subtract from accumulator
vmov_n_f64⚠neon
Duplicate vector element to vector or scalar
vmov_n_p64⚠neon
Duplicate vector element to vector or scalar
vmovl_high_s8⚠neon
Vector move
vmovl_high_s16⚠neon
Vector move
vmovl_high_s32⚠neon
Vector move
vmovl_high_u8⚠neon
Vector move
vmovl_high_u16⚠neon
Vector move
vmovl_high_u32⚠neon
Vector move
vmovn_high_s16⚠neon
Extract narrow
vmovn_high_s32⚠neon
Extract narrow
vmovn_high_s64⚠neon
Extract narrow
vmovn_high_u16⚠neon
Extract narrow
vmovn_high_u32⚠neon
Extract narrow
vmovn_high_u64⚠neon
Extract narrow
vmovq_n_f64⚠neon
Duplicate vector element to vector or scalar
vmovq_n_p64⚠neon
Duplicate vector element to vector or scalar
vmul_f64⚠neon
Multiply
vmul_lane_f64⚠neon
Floating-point multiply
vmul_laneq_f64⚠neon
Floating-point multiply
vmul_n_f64⚠neon
Vector multiply by scalar
vmuld_lane_f64⚠neon
Floating-point multiply
vmuld_laneq_f64⚠neon
Floating-point multiply
vmull_high_lane_s16⚠neon
Multiply long
vmull_high_lane_s32⚠neon
Multiply long
vmull_high_lane_u16⚠neon
Multiply long
vmull_high_lane_u32⚠neon
Multiply long
vmull_high_laneq_s16⚠neon
Multiply long
vmull_high_laneq_s32⚠neon
Multiply long
vmull_high_laneq_u16⚠neon
Multiply long
vmull_high_laneq_u32⚠neon
Multiply long
vmull_high_n_s16⚠neon
Multiply long
vmull_high_n_s32⚠neon
Multiply long
vmull_high_n_u16⚠neon
Multiply long
vmull_high_n_u32⚠neon
Multiply long
vmull_high_p8⚠neon
Polynomial multiply long
vmull_high_p64⚠neon,aes
Polynomial multiply long
vmull_high_s8⚠neon
Signed multiply long
vmull_high_s16⚠neon
Signed multiply long
vmull_high_s32⚠neon
Signed multiply long
vmull_high_u8⚠neon
Unsigned multiply long
vmull_high_u16⚠neon
Unsigned multiply long
vmull_high_u32⚠neon
Unsigned multiply long
vmull_p64⚠neon,aes
Polynomial multiply long
vmulq_f64⚠neon
Multiply
vmulq_lane_f64⚠neon
Floating-point multiply
vmulq_laneq_f64⚠neon
Floating-point multiply
vmulq_n_f64⚠neon
Vector multiply by scalar
vmuls_lane_f32⚠neon
Floating-point multiply
vmuls_laneq_f32⚠neon
Floating-point multiply
vmulx_f32⚠neon
Floating-point multiply extended
vmulx_f64⚠neon
Floating-point multiply extended
vmulx_lane_f32⚠neon
Floating-point multiply extended
vmulx_lane_f64⚠neon
Floating-point multiply extended
vmulx_laneq_f32⚠neon
Floating-point multiply extended
vmulx_laneq_f64⚠neon
Floating-point multiply extended
vmulxd_f64⚠neon
Floating-point multiply extended
vmulxd_lane_f64⚠neon
Floating-point multiply extended
vmulxd_laneq_f64⚠neon
Floating-point multiply extended
vmulxq_f32⚠neon
Floating-point multiply extended
vmulxq_f64⚠neon
Floating-point multiply extended
vmulxq_lane_f32⚠neon
Floating-point multiply extended
vmulxq_lane_f64⚠neon
Floating-point multiply extended
vmulxq_laneq_f32⚠neon
Floating-point multiply extended
vmulxq_laneq_f64⚠neon
Floating-point multiply extended
vmulxs_f32⚠neon
Floating-point multiply extended
vmulxs_lane_f32⚠neon
Floating-point multiply extended
vmulxs_laneq_f32⚠neon
Floating-point multiply extended
vneg_f64⚠neon
Negate
vneg_s64⚠neon
Negate
vnegd_s64⚠neon
Negate
vnegq_f64⚠neon
Negate
vnegq_s64⚠neon
Negate
vpaddd_f64⚠neon
Floating-point add pairwise
vpaddd_s64⚠neon
Add pairwise
vpaddd_u64⚠neon
Add pairwise
vpaddq_f32⚠neon
Floating-point add pairwise
vpaddq_f64⚠neon
Floating-point add pairwise
vpaddq_s8⚠neon
Add pairwise
vpaddq_s16⚠neon
Add pairwise
vpaddq_s32⚠neon
Add pairwise
vpaddq_s64⚠neon
Add pairwise
vpaddq_u8⚠neon
Add pairwise
vpaddq_u16⚠neon
Add pairwise
vpaddq_u32⚠neon
Add pairwise
vpaddq_u64⚠neon
Add pairwise
vpadds_f32⚠neon
Floating-point add pairwise
vpmaxnm_f32⚠neon
Floating-point Maximum Number Pairwise (vector).
vpmaxnmq_f32⚠neon
Floating-point Maximum Number Pairwise (vector).
vpmaxnmq_f64⚠neon
Floating-point Maximum Number Pairwise (vector).
vpmaxnmqd_f64⚠neon
Floating-point maximum number pairwise
vpmaxnms_f32⚠neon
Floating-point maximum number pairwise
vpmaxq_f32⚠neon
Folding maximum of adjacent pairs
vpmaxq_f64⚠neon
Folding maximum of adjacent pairs
vpmaxq_s8⚠neon
Folding maximum of adjacent pairs
vpmaxq_s16⚠neon
Folding maximum of adjacent pairs
vpmaxq_s32⚠neon
Folding maximum of adjacent pairs
vpmaxq_u8⚠neon
Folding maximum of adjacent pairs
vpmaxq_u16⚠neon
Folding maximum of adjacent pairs
vpmaxq_u32⚠neon
Folding maximum of adjacent pairs
vpmaxqd_f64⚠neon
Floating-point maximum pairwise
vpmaxs_f32⚠neon
Floating-point maximum pairwise
vpminnm_f32⚠neon
Floating-point Minimum Number Pairwise (vector).
vpminnmq_f32⚠neon
Floating-point Minimum Number Pairwise (vector).
vpminnmq_f64⚠neon
Floating-point Minimum Number Pairwise (vector).
vpminnmqd_f64⚠neon
Floating-point minimum number pairwise
vpminnms_f32⚠neon
Floating-point minimum number pairwise
vpminq_f32⚠neon
Folding minimum of adjacent pairs
vpminq_f64⚠neon
Folding minimum of adjacent pairs
vpminq_s8⚠neon
Folding minimum of adjacent pairs
vpminq_s16⚠neon
Folding minimum of adjacent pairs
vpminq_s32⚠neon
Folding minimum of adjacent pairs
vpminq_u8⚠neon
Folding minimum of adjacent pairs
vpminq_u16⚠neon
Folding minimum of adjacent pairs
vpminq_u32⚠neon
Folding minimum of adjacent pairs
vpminqd_f64⚠neon
Floating-point minimum pairwise
vpmins_f32⚠neon
Floating-point minimum pairwise
vqabs_s64⚠neon
Singned saturating Absolute value
vqabsb_s8⚠neon
Signed saturating absolute value
vqabsd_s64⚠neon
Signed saturating absolute value
vqabsh_s16⚠neon
Signed saturating absolute value
vqabsq_s64⚠neon
Singned saturating Absolute value
vqabss_s32⚠neon
Signed saturating absolute value
vqaddb_s8⚠neon
Saturating add
vqaddb_u8⚠neon
Saturating add
vqaddd_s64⚠neon
Saturating add
vqaddd_u64⚠neon
Saturating add
vqaddh_s16⚠neon
Saturating add
vqaddh_u16⚠neon
Saturating add
vqadds_s32⚠neon
Saturating add
vqadds_u32⚠neon
Saturating add
vqdmlal_high_lane_s16⚠neon
Signed saturating doubling multiply-add long
vqdmlal_high_lane_s32⚠neon
Signed saturating doubling multiply-add long
vqdmlal_high_laneq_s16⚠neon
Signed saturating doubling multiply-add long
vqdmlal_high_laneq_s32⚠neon
Signed saturating doubling multiply-add long
vqdmlal_high_n_s16⚠neon
Signed saturating doubling multiply-add long
vqdmlal_high_n_s32⚠neon
Signed saturating doubling multiply-add long
vqdmlal_high_s16⚠neon
Signed saturating doubling multiply-add long
vqdmlal_high_s32⚠neon
Signed saturating doubling multiply-add long
vqdmlal_laneq_s16⚠neon
Vector widening saturating doubling multiply accumulate with scalar
vqdmlal_laneq_s32⚠neon
Vector widening saturating doubling multiply accumulate with scalar
vqdmlalh_lane_s16⚠neon
Signed saturating doubling multiply-add long
vqdmlalh_laneq_s16⚠neon
Signed saturating doubling multiply-add long
vqdmlalh_s16⚠neon
Signed saturating doubling multiply-add long
vqdmlals_lane_s32⚠neon
Signed saturating doubling multiply-add long
vqdmlals_laneq_s32⚠neon
Signed saturating doubling multiply-add long
vqdmlals_s32⚠neon
Signed saturating doubling multiply-add long
vqdmlsl_high_lane_s16⚠neon
Signed saturating doubling multiply-subtract long
vqdmlsl_high_lane_s32⚠neon
Signed saturating doubling multiply-subtract long
vqdmlsl_high_laneq_s16⚠neon
Signed saturating doubling multiply-subtract long
vqdmlsl_high_laneq_s32⚠neon
Signed saturating doubling multiply-subtract long
vqdmlsl_high_n_s16⚠neon
Signed saturating doubling multiply-subtract long
vqdmlsl_high_n_s32⚠neon
Signed saturating doubling multiply-subtract long
vqdmlsl_high_s16⚠neon
Signed saturating doubling multiply-subtract long
vqdmlsl_high_s32⚠neon
Signed saturating doubling multiply-subtract long
vqdmlsl_laneq_s16⚠neon
Vector widening saturating doubling multiply subtract with scalar
vqdmlsl_laneq_s32⚠neon
Vector widening saturating doubling multiply subtract with scalar
vqdmlslh_lane_s16⚠neon
Signed saturating doubling multiply-subtract long
vqdmlslh_laneq_s16⚠neon
Signed saturating doubling multiply-subtract long
vqdmlslh_s16⚠neon
Signed saturating doubling multiply-subtract long
vqdmlsls_lane_s32⚠neon
Signed saturating doubling multiply-subtract long
vqdmlsls_laneq_s32⚠neon
Signed saturating doubling multiply-subtract long
vqdmlsls_s32⚠neon
Signed saturating doubling multiply-subtract long
vqdmulh_lane_s16⚠neon
Vector saturating doubling multiply high by scalar
vqdmulh_lane_s32⚠neon
Vector saturating doubling multiply high by scalar
vqdmulhh_lane_s16⚠neon
Signed saturating doubling multiply returning high half
vqdmulhh_laneq_s16⚠neon
Signed saturating doubling multiply returning high half
vqdmulhh_s16⚠neon
Signed saturating doubling multiply returning high half
vqdmulhq_lane_s16⚠neon
Vector saturating doubling multiply high by scalar
vqdmulhq_lane_s32⚠neon
Vector saturating doubling multiply high by scalar
vqdmulhs_lane_s32⚠neon
Signed saturating doubling multiply returning high half
vqdmulhs_laneq_s32⚠neon
Signed saturating doubling multiply returning high half
vqdmulhs_s32⚠neon
Signed saturating doubling multiply returning high half
vqdmull_high_lane_s16⚠neon
Signed saturating doubling multiply long
vqdmull_high_lane_s32⚠neon
Signed saturating doubling multiply long
vqdmull_high_laneq_s16⚠neon
Signed saturating doubling multiply long
vqdmull_high_laneq_s32⚠neon
Signed saturating doubling multiply long
vqdmull_high_n_s16⚠neon
Signed saturating doubling multiply long
vqdmull_high_n_s32⚠neon
Signed saturating doubling multiply long
vqdmull_high_s16⚠neon
Signed saturating doubling multiply long
vqdmull_high_s32⚠neon
Signed saturating doubling multiply long
vqdmull_laneq_s16⚠neon
Vector saturating doubling long multiply by scalar
vqdmull_laneq_s32⚠neon
Vector saturating doubling long multiply by scalar
vqdmullh_lane_s16⚠neon
Signed saturating doubling multiply long
vqdmullh_laneq_s16⚠neon
Signed saturating doubling multiply long
vqdmullh_s16⚠neon
Signed saturating doubling multiply long
vqdmulls_lane_s32⚠neon
Signed saturating doubling multiply long
vqdmulls_laneq_s32⚠neon
Signed saturating doubling multiply long
vqdmulls_s32⚠neon
Signed saturating doubling multiply long
vqmovn_high_s16⚠neon
Signed saturating extract narrow
vqmovn_high_s32⚠neon
Signed saturating extract narrow
vqmovn_high_s64⚠neon
Signed saturating extract narrow
vqmovn_high_u16⚠neon
Signed saturating extract narrow
vqmovn_high_u32⚠neon
Signed saturating extract narrow
vqmovn_high_u64⚠neon
Signed saturating extract narrow
vqmovnd_s64⚠neon
Saturating extract narrow
vqmovnd_u64⚠neon
Saturating extract narrow
vqmovnh_s16⚠neon
Saturating extract narrow
vqmovnh_u16⚠neon
Saturating extract narrow
vqmovns_s32⚠neon
Saturating extract narrow
vqmovns_u32⚠neon
Saturating extract narrow
vqmovun_high_s16⚠neon
Signed saturating extract unsigned narrow
vqmovun_high_s32⚠neon
Signed saturating extract unsigned narrow
vqmovun_high_s64⚠neon
Signed saturating extract unsigned narrow
vqmovund_s64⚠neon
Signed saturating extract unsigned narrow
vqmovunh_s16⚠neon
Signed saturating extract unsigned narrow
vqmovuns_s32⚠neon
Signed saturating extract unsigned narrow
vqneg_s64⚠neon
Signed saturating negate
vqnegb_s8⚠neon
Signed saturating negate
vqnegd_s64⚠neon
Signed saturating negate
vqnegh_s16⚠neon
Signed saturating negate
vqnegq_s64⚠neon
Signed saturating negate
vqnegs_s32⚠neon
Signed saturating negate
vqrdmlah_lane_s16⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlah_lane_s32⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlah_laneq_s16⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlah_laneq_s32⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlah_s16⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlah_s32⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahh_lane_s16⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahh_laneq_s16⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahh_s16⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahq_lane_s16⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahq_lane_s32⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahq_laneq_s16⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahq_laneq_s32⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahq_s16⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahq_s32⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahs_lane_s32⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahs_laneq_s32⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlahs_s32⚠rdm
Signed saturating rounding doubling multiply accumulate returning high half
vqrdmlsh_lane_s16⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlsh_lane_s32⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlsh_laneq_s16⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlsh_laneq_s32⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlsh_s16⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlsh_s32⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshh_lane_s16⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshh_laneq_s16⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshh_s16⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshq_lane_s16⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshq_lane_s32⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshq_laneq_s16⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshq_laneq_s32⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshq_s16⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshq_s32⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshs_lane_s32⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshs_laneq_s32⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmlshs_s32⚠rdm
Signed saturating rounding doubling multiply subtract returning high half
vqrdmulhh_lane_s16⚠neon
Signed saturating rounding doubling multiply returning high half
vqrdmulhh_laneq_s16⚠neon
Signed saturating rounding doubling multiply returning high half
vqrdmulhh_s16⚠neon
Signed saturating rounding doubling multiply returning high half
vqrdmulhs_lane_s32⚠neon
Signed saturating rounding doubling multiply returning high half
vqrdmulhs_laneq_s32⚠neon
Signed saturating rounding doubling multiply returning high half
vqrdmulhs_s32⚠neon
Signed saturating rounding doubling multiply returning high half
vqrshlb_s8⚠neon
Signed saturating rounding shift left
vqrshlb_u8⚠neon
Unsigned signed saturating rounding shift left
vqrshld_s64⚠neon
Signed saturating rounding shift left
vqrshld_u64⚠neon
Unsigned signed saturating rounding shift left
vqrshlh_s16⚠neon
Signed saturating rounding shift left
vqrshlh_u16⚠neon
Unsigned signed saturating rounding shift left
vqrshls_s32⚠neon
Signed saturating rounding shift left
vqrshls_u32⚠neon
Unsigned signed saturating rounding shift left
vqrshrn_high_n_s16⚠neon
Signed saturating rounded shift right narrow
vqrshrn_high_n_s32⚠neon
Signed saturating rounded shift right narrow
vqrshrn_high_n_s64⚠neon
Signed saturating rounded shift right narrow
vqrshrn_high_n_u16⚠neon
Unsigned saturating rounded shift right narrow
vqrshrn_high_n_u32⚠neon
Unsigned saturating rounded shift right narrow
vqrshrn_high_n_u64⚠neon
Unsigned saturating rounded shift right narrow
vqrshrnd_n_s64⚠neon
Signed saturating rounded shift right narrow
vqrshrnd_n_u64⚠neon
Unsigned saturating rounded shift right narrow
vqrshrnh_n_s16⚠neon
Signed saturating rounded shift right narrow
vqrshrnh_n_u16⚠neon
Unsigned saturating rounded shift right narrow
vqrshrns_n_s32⚠neon
Signed saturating rounded shift right narrow
vqrshrns_n_u32⚠neon
Unsigned saturating rounded shift right narrow
vqrshrun_high_n_s16⚠neon
Signed saturating rounded shift right unsigned narrow
vqrshrun_high_n_s32⚠neon
Signed saturating rounded shift right unsigned narrow
vqrshrun_high_n_s64⚠neon
Signed saturating rounded shift right unsigned narrow
vqrshrund_n_s64⚠neon
Signed saturating rounded shift right unsigned narrow
vqrshrunh_n_s16⚠neon
Signed saturating rounded shift right unsigned narrow
vqrshruns_n_s32⚠neon
Signed saturating rounded shift right unsigned narrow
vqshlb_n_s8⚠neon
Signed saturating shift left
vqshlb_n_u8⚠neon
Unsigned saturating shift left
vqshlb_s8⚠neon
Signed saturating shift left
vqshlb_u8⚠neon
Unsigned saturating shift left
vqshld_n_s64⚠neon
Signed saturating shift left
vqshld_n_u64⚠neon
Unsigned saturating shift left
vqshld_s64⚠neon
Signed saturating shift left
vqshld_u64⚠neon
Unsigned saturating shift left
vqshlh_n_s16⚠neon
Signed saturating shift left
vqshlh_n_u16⚠neon
Unsigned saturating shift left
vqshlh_s16⚠neon
Signed saturating shift left
vqshlh_u16⚠neon
Unsigned saturating shift left
vqshls_n_s32⚠neon
Signed saturating shift left
vqshls_n_u32⚠neon
Unsigned saturating shift left
vqshls_s32⚠neon
Signed saturating shift left
vqshls_u32⚠neon
Unsigned saturating shift left
vqshlub_n_s8⚠neon
Signed saturating shift left unsigned
vqshlud_n_s64⚠neon
Signed saturating shift left unsigned
vqshluh_n_s16⚠neon
Signed saturating shift left unsigned
vqshlus_n_s32⚠neon
Signed saturating shift left unsigned
vqshrn_high_n_s16⚠neon
Signed saturating shift right narrow
vqshrn_high_n_s32⚠neon
Signed saturating shift right narrow
vqshrn_high_n_s64⚠neon
Signed saturating shift right narrow
vqshrn_high_n_u16⚠neon
Unsigned saturating shift right narrow
vqshrn_high_n_u32⚠neon
Unsigned saturating shift right narrow
vqshrn_high_n_u64⚠neon
Unsigned saturating shift right narrow
vqshrnd_n_s64⚠neon
Signed saturating shift right narrow
vqshrnd_n_u64⚠neon
Unsigned saturating shift right narrow
vqshrnh_n_s16⚠neon
Signed saturating shift right narrow
vqshrnh_n_u16⚠neon
Unsigned saturating shift right narrow
vqshrns_n_s32⚠neon
Signed saturating shift right narrow
vqshrns_n_u32⚠neon
Unsigned saturating shift right narrow
vqshrun_high_n_s16⚠neon
Signed saturating shift right unsigned narrow
vqshrun_high_n_s32⚠neon
Signed saturating shift right unsigned narrow
vqshrun_high_n_s64⚠neon
Signed saturating shift right unsigned narrow
vqshrund_n_s64⚠neon
Signed saturating shift right unsigned narrow
vqshrunh_n_s16⚠neon
Signed saturating shift right unsigned narrow
vqshruns_n_s32⚠neon
Signed saturating shift right unsigned narrow
vqsubb_s8⚠neon
Saturating subtract
vqsubb_u8⚠neon
Saturating subtract
vqsubd_s64⚠neon
Saturating subtract
vqsubd_u64⚠neon
Saturating subtract
vqsubh_s16⚠neon
Saturating subtract
vqsubh_u16⚠neon
Saturating subtract
vqsubs_s32⚠neon
Saturating subtract
vqsubs_u32⚠neon
Saturating subtract
vqtbl1_p8⚠neon
Table look-up
vqtbl1_s8⚠neon
Table look-up
vqtbl1_u8⚠neon
Table look-up
vqtbl1q_p8⚠neon
Table look-up
vqtbl1q_s8⚠neon
Table look-up
vqtbl1q_u8⚠neon
Table look-up
vqtbl2_p8⚠neon
Table look-up
vqtbl2_s8⚠neon
Table look-up
vqtbl2_u8⚠neon
Table look-up
vqtbl2q_p8⚠neon
Table look-up
vqtbl2q_s8⚠neon
Table look-up
vqtbl2q_u8⚠neon
Table look-up
vqtbl3_p8⚠neon
Table look-up
vqtbl3_s8⚠neon
Table look-up
vqtbl3_u8⚠neon
Table look-up
vqtbl3q_p8⚠neon
Table look-up
vqtbl3q_s8⚠neon
Table look-up
vqtbl3q_u8⚠neon
Table look-up
vqtbl4_p8⚠neon
Table look-up
vqtbl4_s8⚠neon
Table look-up
vqtbl4_u8⚠neon
Table look-up
vqtbl4q_p8⚠neon
Table look-up
vqtbl4q_s8⚠neon
Table look-up
vqtbl4q_u8⚠neon
Table look-up
vqtbx1_p8⚠neon
Extended table look-up
vqtbx1_s8⚠neon
Extended table look-up
vqtbx1_u8⚠neon
Extended table look-up
vqtbx1q_p8⚠neon
Extended table look-up
vqtbx1q_s8⚠neon
Extended table look-up
vqtbx1q_u8⚠neon
Extended table look-up
vqtbx2_p8⚠neon
Extended table look-up
vqtbx2_s8⚠neon
Extended table look-up
vqtbx2_u8⚠neon
Extended table look-up
vqtbx2q_p8⚠neon
Extended table look-up
vqtbx2q_s8⚠neon
Extended table look-up
vqtbx2q_u8⚠neon
Extended table look-up
vqtbx3_p8⚠neon
Extended table look-up
vqtbx3_s8⚠neon
Extended table look-up
vqtbx3_u8⚠neon
Extended table look-up
vqtbx3q_p8⚠neon
Extended table look-up
vqtbx3q_s8⚠neon
Extended table look-up
vqtbx3q_u8⚠neon
Extended table look-up
vqtbx4_p8⚠neon
Extended table look-up
vqtbx4_s8⚠neon
Extended table look-up
vqtbx4_u8⚠neon
Extended table look-up
vqtbx4q_p8⚠neon
Extended table look-up
vqtbx4q_s8⚠neon
Extended table look-up
vqtbx4q_u8⚠neon
Extended table look-up
vrbit_p8⚠neon
Reverse bit order
vrbit_s8⚠neon
Reverse bit order
vrbit_u8⚠neon
Reverse bit order
vrbitq_p8⚠neon
Reverse bit order
vrbitq_s8⚠neon
Reverse bit order
vrbitq_u8⚠neon
Reverse bit order
vrecpe_f64⚠neon
Reciprocal estimate.
vrecped_f64⚠neon
Reciprocal estimate.
vrecpeq_f64⚠neon
Reciprocal estimate.
vrecpes_f32⚠neon
Reciprocal estimate.
vrecps_f64⚠neon
Floating-point reciprocal step
vrecpsd_f64⚠neon
Floating-point reciprocal step
vrecpsq_f64⚠neon
Floating-point reciprocal step
vrecpss_f32⚠neon
Floating-point reciprocal step
vrecpxd_f64⚠neon
Floating-point reciprocal exponent
vrecpxs_f32⚠neon
Floating-point reciprocal exponent
vreinterpret_f32_f64⚠neon
Vector reinterpret cast operation
vreinterpret_f32_p64⚠neon
Vector reinterpret cast operation
vreinterpret_f64_f32⚠neon
Vector reinterpret cast operation
vreinterpret_f64_p8⚠neon
Vector reinterpret cast operation
vreinterpret_f64_p16⚠neon
Vector reinterpret cast operation
vreinterpret_f64_p64⚠neon
Vector reinterpret cast operation
vreinterpret_f64_s8⚠neon
Vector reinterpret cast operation
vreinterpret_f64_s16⚠neon
Vector reinterpret cast operation
vreinterpret_f64_s32⚠neon
Vector reinterpret cast operation
vreinterpret_f64_s64⚠neon
Vector reinterpret cast operation
vreinterpret_f64_u8⚠neon
Vector reinterpret cast operation
vreinterpret_f64_u16⚠neon
Vector reinterpret cast operation
vreinterpret_f64_u32⚠neon
Vector reinterpret cast operation
vreinterpret_f64_u64⚠neon
Vector reinterpret cast operation
vreinterpret_p8_f64⚠neon
Vector reinterpret cast operation
vreinterpret_p16_f64⚠neon
Vector reinterpret cast operation
vreinterpret_p64_f32⚠neon
Vector reinterpret cast operation
vreinterpret_p64_f64⚠neon
Vector reinterpret cast operation
vreinterpret_p64_s64⚠neon
Vector reinterpret cast operation
vreinterpret_p64_u64⚠neon
Vector reinterpret cast operation
vreinterpret_s8_f64⚠neon
Vector reinterpret cast operation
vreinterpret_s16_f64⚠neon
Vector reinterpret cast operation
vreinterpret_s32_f64⚠neon
Vector reinterpret cast operation
vreinterpret_s64_f64⚠neon
Vector reinterpret cast operation
vreinterpret_s64_p64⚠neon
Vector reinterpret cast operation
vreinterpret_u8_f64⚠neon
Vector reinterpret cast operation
vreinterpret_u16_f64⚠neon
Vector reinterpret cast operation
vreinterpret_u32_f64⚠neon
Vector reinterpret cast operation
vreinterpret_u64_f64⚠neon
Vector reinterpret cast operation
vreinterpret_u64_p64⚠neon
Vector reinterpret cast operation
vreinterpretq_f32_f64⚠neon
Vector reinterpret cast operation
vreinterpretq_f32_p64⚠neon
Vector reinterpret cast operation
vreinterpretq_f64_f32⚠neon
Vector reinterpret cast operation
vreinterpretq_f64_p8⚠neon
Vector reinterpret cast operation
vreinterpretq_f64_p16⚠neon
Vector reinterpret cast operation
vreinterpretq_f64_p64⚠neon
Vector reinterpret cast operation
vreinterpretq_f64_p128⚠neon
Vector reinterpret cast operation
vreinterpretq_f64_s8⚠neon
Vector reinterpret cast operation
vreinterpretq_f64_s16⚠neon
Vector reinterpret cast operation
vreinterpretq_f64_s32⚠neon
Vector reinterpret cast operation
vreinterpretq_f64_s64⚠neon
Vector reinterpret cast operation
vreinterpretq_f64_u8⚠neon
Vector reinterpret cast operation
vreinterpretq_f64_u16⚠neon
Vector reinterpret cast operation
vreinterpretq_f64_u32⚠neon
Vector reinterpret cast operation
vreinterpretq_f64_u64⚠neon
Vector reinterpret cast operation
vreinterpretq_p8_f64⚠neon
Vector reinterpret cast operation
vreinterpretq_p16_f64⚠neon
Vector reinterpret cast operation
vreinterpretq_p64_f32⚠neon
Vector reinterpret cast operation
vreinterpretq_p64_f64⚠neon
Vector reinterpret cast operation
vreinterpretq_p64_s64⚠neon
Vector reinterpret cast operation
vreinterpretq_p64_u64⚠neon
Vector reinterpret cast operation
vreinterpretq_p128_f64⚠neon
Vector reinterpret cast operation
vreinterpretq_s8_f64⚠neon
Vector reinterpret cast operation
vreinterpretq_s16_f64⚠neon
Vector reinterpret cast operation
vreinterpretq_s32_f64⚠neon
Vector reinterpret cast operation
vreinterpretq_s64_f64⚠neon
Vector reinterpret cast operation
vreinterpretq_s64_p64⚠neon
Vector reinterpret cast operation
vreinterpretq_u8_f64⚠neon
Vector reinterpret cast operation
vreinterpretq_u16_f64⚠neon
Vector reinterpret cast operation
vreinterpretq_u32_f64⚠neon
Vector reinterpret cast operation
vreinterpretq_u64_f64⚠neon
Vector reinterpret cast operation
vreinterpretq_u64_p64⚠neon
Vector reinterpret cast operation
vrnd_f32⚠neon
Floating-point round to integral, toward zero
vrnd_f64⚠neon
Floating-point round to integral, toward zero
vrnda_f32⚠neon
Floating-point round to integral, to nearest with ties to away
vrnda_f64⚠neon
Floating-point round to integral, to nearest with ties to away
vrndaq_f32⚠neon
Floating-point round to integral, to nearest with ties to away
vrndaq_f64⚠neon
Floating-point round to integral, to nearest with ties to away
vrndi_f32⚠neon
Floating-point round to integral, using current rounding mode
vrndi_f64⚠neon
Floating-point round to integral, using current rounding mode
vrndiq_f32⚠neon
Floating-point round to integral, using current rounding mode
vrndiq_f64⚠neon
Floating-point round to integral, using current rounding mode
vrndm_f32⚠neon
Floating-point round to integral, toward minus infinity
vrndm_f64⚠neon
Floating-point round to integral, toward minus infinity
vrndmq_f32⚠neon
Floating-point round to integral, toward minus infinity
vrndmq_f64⚠neon
Floating-point round to integral, toward minus infinity
vrndn_f64⚠neon
Floating-point round to integral, to nearest with ties to even
vrndnq_f64⚠neon
Floating-point round to integral, to nearest with ties to even
vrndns_f32⚠neon
Floating-point round to integral, to nearest with ties to even
vrndp_f32⚠neon
Floating-point round to integral, toward plus infinity
vrndp_f64⚠neon
Floating-point round to integral, toward plus infinity
vrndpq_f32⚠neon
Floating-point round to integral, toward plus infinity
vrndpq_f64⚠neon
Floating-point round to integral, toward plus infinity
vrndq_f32⚠neon
Floating-point round to integral, toward zero
vrndq_f64⚠neon
Floating-point round to integral, toward zero
vrndx_f32⚠neon
Floating-point round to integral exact, using current rounding mode
vrndx_f64⚠neon
Floating-point round to integral exact, using current rounding mode
vrndxq_f32⚠neon
Floating-point round to integral exact, using current rounding mode
vrndxq_f64⚠neon
Floating-point round to integral exact, using current rounding mode
vrshld_s64⚠neon
Signed rounding shift left
vrshld_u64⚠neon
Unsigned rounding shift left
vrshrd_n_s64⚠neon
Signed rounding shift right
vrshrd_n_u64⚠neon
Unsigned rounding shift right
vrshrn_high_n_s16⚠neon
Rounding shift right narrow
vrshrn_high_n_s32⚠neon
Rounding shift right narrow
vrshrn_high_n_s64⚠neon
Rounding shift right narrow
vrshrn_high_n_u16⚠neon
Rounding shift right narrow
vrshrn_high_n_u32⚠neon
Rounding shift right narrow
vrshrn_high_n_u64⚠neon
Rounding shift right narrow
vrsqrte_f64⚠neon
Reciprocal square-root estimate.
vrsqrted_f64⚠neon
Reciprocal square-root estimate.
vrsqrteq_f64⚠neon
Reciprocal square-root estimate.
vrsqrtes_f32⚠neon
Reciprocal square-root estimate.
vrsqrts_f64⚠neon
Floating-point reciprocal square root step
vrsqrtsd_f64⚠neon
Floating-point reciprocal square root step
vrsqrtsq_f64⚠neon
Floating-point reciprocal square root step
vrsqrtss_f32⚠neon
Floating-point reciprocal square root step
vrsrad_n_s64⚠neon
Signed rounding shift right and accumulate.
vrsrad_n_u64⚠neon
Ungisned rounding shift right and accumulate.
vrsubhn_high_s16⚠neon
Rounding subtract returning high narrow
vrsubhn_high_s32⚠neon
Rounding subtract returning high narrow
vrsubhn_high_s64⚠neon
Rounding subtract returning high narrow
vrsubhn_high_u16⚠neon
Rounding subtract returning high narrow
vrsubhn_high_u32⚠neon
Rounding subtract returning high narrow
vrsubhn_high_u64⚠neon
Rounding subtract returning high narrow
vset_lane_f64⚠neon
Insert vector element from another vector element
vsetq_lane_f64⚠neon
Insert vector element from another vector element
vshld_n_s64⚠neon
Shift left
vshld_n_u64⚠neon
Shift left
vshld_s64⚠neon
Signed Shift left
vshld_u64⚠neon
Unsigned Shift left
vshll_high_n_s8⚠neon
Signed shift left long
vshll_high_n_s16⚠neon
Signed shift left long
vshll_high_n_s32⚠neon
Signed shift left long
vshll_high_n_u8⚠neon
Signed shift left long
vshll_high_n_u16⚠neon
Signed shift left long
vshll_high_n_u32⚠neon
Signed shift left long
vshrd_n_s64⚠neon
Signed shift right
vshrd_n_u64⚠neon
Unsigned shift right
vshrn_high_n_s16⚠neon
Shift right narrow
vshrn_high_n_s32⚠neon
Shift right narrow
vshrn_high_n_s64⚠neon
Shift right narrow
vshrn_high_n_u16⚠neon
Shift right narrow
vshrn_high_n_u32⚠neon
Shift right narrow
vshrn_high_n_u64⚠neon
Shift right narrow
vsli_n_p8⚠neon
Shift Left and Insert (immediate)
vsli_n_p16⚠neon
Shift Left and Insert (immediate)
vsli_n_p64⚠neon,aes
Shift Left and Insert (immediate)
vsli_n_s8⚠neon
Shift Left and Insert (immediate)
vsli_n_s16⚠neon
Shift Left and Insert (immediate)
vsli_n_s32⚠neon
Shift Left and Insert (immediate)
vsli_n_s64⚠neon
Shift Left and Insert (immediate)
vsli_n_u8⚠neon
Shift Left and Insert (immediate)
vsli_n_u16⚠neon
Shift Left and Insert (immediate)
vsli_n_u32⚠neon
Shift Left and Insert (immediate)
vsli_n_u64⚠neon
Shift Left and Insert (immediate)
vslid_n_s64⚠neon
Shift left and insert
vslid_n_u64⚠neon
Shift left and insert
vsliq_n_p8⚠neon
Shift Left and Insert (immediate)
vsliq_n_p16⚠neon
Shift Left and Insert (immediate)
vsliq_n_p64⚠neon,aes
Shift Left and Insert (immediate)
vsliq_n_s8⚠neon
Shift Left and Insert (immediate)
vsliq_n_s16⚠neon
Shift Left and Insert (immediate)
vsliq_n_s32⚠neon
Shift Left and Insert (immediate)
vsliq_n_s64⚠neon
Shift Left and Insert (immediate)
vsliq_n_u8⚠neon
Shift Left and Insert (immediate)
vsliq_n_u16⚠neon
Shift Left and Insert (immediate)
vsliq_n_u32⚠neon
Shift Left and Insert (immediate)
vsliq_n_u64⚠neon
Shift Left and Insert (immediate)
vsqadd_u8⚠neon
Unsigned saturating Accumulate of Signed value.
vsqadd_u16⚠neon
Unsigned saturating Accumulate of Signed value.
vsqadd_u32⚠neon
Unsigned saturating Accumulate of Signed value.
vsqadd_u64⚠neon
Unsigned saturating Accumulate of Signed value.
vsqaddb_u8⚠neon
Unsigned saturating accumulate of signed value
vsqaddd_u64⚠neon
Unsigned saturating accumulate of signed value
vsqaddh_u16⚠neon
Unsigned saturating accumulate of signed value
vsqaddq_u8⚠neon
Unsigned saturating Accumulate of Signed value.
vsqaddq_u16⚠neon
Unsigned saturating Accumulate of Signed value.
vsqaddq_u32⚠neon
Unsigned saturating Accumulate of Signed value.
vsqaddq_u64⚠neon
Unsigned saturating Accumulate of Signed value.
vsqadds_u32⚠neon
Unsigned saturating accumulate of signed value
vsqrt_f32⚠neon
Calculates the square root of each lane.
vsqrt_f64⚠neon
Calculates the square root of each lane.
vsqrtq_f32⚠neon
Calculates the square root of each lane.
vsqrtq_f64⚠neon
Calculates the square root of each lane.
vsrad_n_s64⚠neon
Signed shift right and accumulate
vsrad_n_u64⚠neon
Unsigned shift right and accumulate
vsri_n_p8⚠neon
Shift Right and Insert (immediate)
vsri_n_p16⚠neon
Shift Right and Insert (immediate)
vsri_n_p64⚠neon,aes
Shift Right and Insert (immediate)
vsri_n_s8⚠neon
Shift Right and Insert (immediate)
vsri_n_s16⚠neon
Shift Right and Insert (immediate)
vsri_n_s32⚠neon
Shift Right and Insert (immediate)
vsri_n_s64⚠neon
Shift Right and Insert (immediate)
vsri_n_u8⚠neon
Shift Right and Insert (immediate)
vsri_n_u16⚠neon
Shift Right and Insert (immediate)
vsri_n_u32⚠neon
Shift Right and Insert (immediate)
vsri_n_u64⚠neon
Shift Right and Insert (immediate)
vsrid_n_s64⚠neon
Shift right and insert
vsrid_n_u64⚠neon
Shift right and insert
vsriq_n_p8⚠neon
Shift Right and Insert (immediate)
vsriq_n_p16⚠neon
Shift Right and Insert (immediate)
vsriq_n_p64⚠neon,aes
Shift Right and Insert (immediate)
vsriq_n_s8⚠neon
Shift Right and Insert (immediate)
vsriq_n_s16⚠neon
Shift Right and Insert (immediate)
vsriq_n_s32⚠neon
Shift Right and Insert (immediate)
vsriq_n_s64⚠neon
Shift Right and Insert (immediate)
vsriq_n_u8⚠neon
Shift Right and Insert (immediate)
vsriq_n_u16⚠neon
Shift Right and Insert (immediate)
vsriq_n_u32⚠neon
Shift Right and Insert (immediate)
vsriq_n_u64⚠neon
Shift Right and Insert (immediate)
vst1_f32⚠neon
vst1_f64⚠neon
vst1_f64_x2⚠neon
Store multiple single-element structures to one, two, three, or four registers
vst1_f64_x3⚠neon
Store multiple single-element structures to one, two, three, or four registers
vst1_f64_x4⚠neon
Store multiple single-element structures to one, two, three, or four registers
vst1_lane_f64⚠neon
Store multiple single-element structures from one, two, three, or four registers
vst1_p8⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_p16⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_p64⚠neon,aes
Arm’s documentation
vst1_s8⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_s16⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_s32⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_s64⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_u8⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_u16⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_u32⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1_u64⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_f32⚠neon
vst1q_f64⚠neon
vst1q_f64_x2⚠neon
Store multiple single-element structures to one, two, three, or four registers
vst1q_f64_x3⚠neon
Store multiple single-element structures to one, two, three, or four registers
vst1q_f64_x4⚠neon
Store multiple single-element structures to one, two, three, or four registers
vst1q_lane_f64⚠neon
Store multiple single-element structures from one, two, three, or four registers
vst1q_p8⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_p16⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_p64⚠neon,aes
Arm’s documentation
vst1q_s8⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_s16⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_s32⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_s64⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_u8⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_u16⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_u32⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst1q_u64⚠neon
Store multiple single-element structures from one, two, three, or four registers.
vst2_f64⚠neon
Store multiple 2-element structures from two registers
vst2_lane_f64⚠neon
Store multiple 2-element structures from two registers
vst2_lane_p64⚠neon,aes
Store multiple 2-element structures from two registers
vst2_lane_s64⚠neon
Store multiple 2-element structures from two registers
vst2_lane_u64⚠neon
Store multiple 2-element structures from two registers
vst2q_f64⚠neon
Store multiple 2-element structures from two registers
vst2q_lane_f64⚠neon
Store multiple 2-element structures from two registers
vst2q_lane_p8⚠neon
Store multiple 2-element structures from two registers
vst2q_lane_p64⚠neon,aes
Store multiple 2-element structures from two registers
vst2q_lane_s8⚠neon
Store multiple 2-element structures from two registers
vst2q_lane_s64⚠neon
Store multiple 2-element structures from two registers
vst2q_lane_u8⚠neon
Store multiple 2-element structures from two registers
vst2q_lane_u64⚠neon
Store multiple 2-element structures from two registers
vst2q_p64⚠neon,aes
Store multiple 2-element structures from two registers
vst2q_s64⚠neon
Store multiple 2-element structures from two registers
vst2q_u64⚠neon
Store multiple 2-element structures from two registers
vst3_f64⚠neon
Store multiple 3-element structures from three registers
vst3_lane_f64⚠neon
Store multiple 3-element structures from three registers
vst3_lane_p64⚠neon,aes
Store multiple 3-element structures from three registers
vst3_lane_s64⚠neon
Store multiple 3-element structures from three registers
vst3_lane_u64⚠neon
Store multiple 3-element structures from three registers
vst3q_f64⚠neon
Store multiple 3-element structures from three registers
vst3q_lane_f64⚠neon
Store multiple 3-element structures from three registers
vst3q_lane_p8⚠neon
Store multiple 3-element structures from three registers
vst3q_lane_p64⚠neon,aes
Store multiple 3-element structures from three registers
vst3q_lane_s8⚠neon
Store multiple 3-element structures from three registers
vst3q_lane_s64⚠neon
Store multiple 3-element structures from three registers
vst3q_lane_u8⚠neon
Store multiple 3-element structures from three registers
vst3q_lane_u64⚠neon
Store multiple 3-element structures from three registers
vst3q_p64⚠neon,aes
Store multiple 3-element structures from three registers
vst3q_s64⚠neon
Store multiple 3-element structures from three registers
vst3q_u64⚠neon
Store multiple 3-element structures from three registers
vst4_f64⚠neon
Store multiple 4-element structures from four registers
vst4_lane_f64⚠neon
Store multiple 4-element structures from four registers
vst4_lane_p64⚠neon,aes
Store multiple 4-element structures from four registers
vst4_lane_s64⚠neon
Store multiple 4-element structures from four registers
vst4_lane_u64⚠neon
Store multiple 4-element structures from four registers
vst4q_f64⚠neon
Store multiple 4-element structures from four registers
vst4q_lane_f64⚠neon
Store multiple 4-element structures from four registers
vst4q_lane_p8⚠neon
Store multiple 4-element structures from four registers
vst4q_lane_p64⚠neon,aes
Store multiple 4-element structures from four registers
vst4q_lane_s8⚠neon
Store multiple 4-element structures from four registers
vst4q_lane_s64⚠neon
Store multiple 4-element structures from four registers
vst4q_lane_u8⚠neon
Store multiple 4-element structures from four registers
vst4q_lane_u64⚠neon
Store multiple 4-element structures from four registers
vst4q_p64⚠neon,aes
Store multiple 4-element structures from four registers
vst4q_s64⚠neon
Store multiple 4-element structures from four registers
vst4q_u64⚠neon
Store multiple 4-element structures from four registers
vsub_f64⚠neon
Subtract
vsubd_s64⚠neon
Subtract
vsubd_u64⚠neon
Subtract
vsubl_high_s8⚠neon
Signed Subtract Long
vsubl_high_s16⚠neon
Signed Subtract Long
vsubl_high_s32⚠neon
Signed Subtract Long
vsubl_high_u8⚠neon
Unsigned Subtract Long
vsubl_high_u16⚠neon
Unsigned Subtract Long
vsubl_high_u32⚠neon
Unsigned Subtract Long
vsubq_f64⚠neon
Subtract
vsubw_high_s8⚠neon
Signed Subtract Wide
vsubw_high_s16⚠neon
Signed Subtract Wide
vsubw_high_s32⚠neon
Signed Subtract Wide
vsubw_high_u8⚠neon
Unsigned Subtract Wide
vsubw_high_u16⚠neon
Unsigned Subtract Wide
vsubw_high_u32⚠neon
Unsigned Subtract Wide
vtbl1_p8⚠neon
Table look-up
vtbl1_s8⚠neon
Table look-up
vtbl1_u8⚠neon
Table look-up
vtbl2_p8⚠neon
Table look-up
vtbl2_s8⚠neon
Table look-up
vtbl2_u8⚠neon
Table look-up
vtbl3_p8⚠neon
Table look-up
vtbl3_s8⚠neon
Table look-up
vtbl3_u8⚠neon
Table look-up
vtbl4_p8⚠neon
Table look-up
vtbl4_s8⚠neon
Table look-up
vtbl4_u8⚠neon
Table look-up
vtbx1_p8⚠neon
Extended table look-up
vtbx1_s8⚠neon
Extended table look-up
vtbx1_u8⚠neon
Extended table look-up
vtbx2_p8⚠neon
Extended table look-up
vtbx2_s8⚠neon
Extended table look-up
vtbx2_u8⚠neon
Extended table look-up
vtbx3_p8⚠neon
Extended table look-up
vtbx3_s8⚠neon
Extended table look-up
vtbx3_u8⚠neon
Extended table look-up
vtbx4_p8⚠neon
Extended table look-up
vtbx4_s8⚠neon
Extended table look-up
vtbx4_u8⚠neon
Extended table look-up
vtrn1_f32⚠neon
Transpose vectors
vtrn1_p8⚠neon
Transpose vectors
vtrn1_p16⚠neon
Transpose vectors
vtrn1_s8⚠neon
Transpose vectors
vtrn1_s16⚠neon
Transpose vectors
vtrn1_s32⚠neon
Transpose vectors
vtrn1_u8⚠neon
Transpose vectors
vtrn1_u16⚠neon
Transpose vectors
vtrn1_u32⚠neon
Transpose vectors
vtrn1q_f32⚠neon
Transpose vectors
vtrn1q_f64⚠neon
Transpose vectors
vtrn1q_p8⚠neon
Transpose vectors
vtrn1q_p16⚠neon
Transpose vectors
vtrn1q_p64⚠neon
Transpose vectors
vtrn1q_s8⚠neon
Transpose vectors
vtrn1q_s16⚠neon
Transpose vectors
vtrn1q_s32⚠neon
Transpose vectors
vtrn1q_s64⚠neon
Transpose vectors
vtrn1q_u8⚠neon
Transpose vectors
vtrn1q_u16⚠neon
Transpose vectors
vtrn1q_u32⚠neon
Transpose vectors
vtrn1q_u64⚠neon
Transpose vectors
vtrn2_f32⚠neon
Transpose vectors
vtrn2_p8⚠neon
Transpose vectors
vtrn2_p16⚠neon
Transpose vectors
vtrn2_s8⚠neon
Transpose vectors
vtrn2_s16⚠neon
Transpose vectors
vtrn2_s32⚠neon
Transpose vectors
vtrn2_u8⚠neon
Transpose vectors
vtrn2_u16⚠neon
Transpose vectors
vtrn2_u32⚠neon
Transpose vectors
vtrn2q_f32⚠neon
Transpose vectors
vtrn2q_f64⚠neon
Transpose vectors
vtrn2q_p8⚠neon
Transpose vectors
vtrn2q_p16⚠neon
Transpose vectors
vtrn2q_p64⚠neon
Transpose vectors
vtrn2q_s8⚠neon
Transpose vectors
vtrn2q_s16⚠neon
Transpose vectors
vtrn2q_s32⚠neon
Transpose vectors
vtrn2q_s64⚠neon
Transpose vectors
vtrn2q_u8⚠neon
Transpose vectors
vtrn2q_u16⚠neon
Transpose vectors
vtrn2q_u32⚠neon
Transpose vectors
vtrn2q_u64⚠neon
Transpose vectors
vtst_p64⚠neon
Signed compare bitwise Test bits nonzero
vtst_s64⚠neon
Signed compare bitwise Test bits nonzero
vtst_u64⚠neon
Unsigned compare bitwise Test bits nonzero
vtstd_s64⚠neon
Compare bitwise test bits nonzero
vtstd_u64⚠neon
Compare bitwise test bits nonzero
vtstq_p64⚠neon
Signed compare bitwise Test bits nonzero
vtstq_s64⚠neon
Signed compare bitwise Test bits nonzero
vtstq_u64⚠neon
Unsigned compare bitwise Test bits nonzero
vuqadd_s8⚠neon
Signed saturating Accumulate of Unsigned value.
vuqadd_s16⚠neon
Signed saturating Accumulate of Unsigned value.
vuqadd_s32⚠neon
Signed saturating Accumulate of Unsigned value.
vuqadd_s64⚠neon
Signed saturating Accumulate of Unsigned value.
vuqaddb_s8⚠neon
Signed saturating accumulate of unsigned value
vuqaddd_s64⚠neon
Signed saturating accumulate of unsigned value
vuqaddh_s16⚠neon
Signed saturating accumulate of unsigned value
vuqaddq_s8⚠neon
Signed saturating Accumulate of Unsigned value.
vuqaddq_s16⚠neon
Signed saturating Accumulate of Unsigned value.
vuqaddq_s32⚠neon
Signed saturating Accumulate of Unsigned value.
vuqaddq_s64⚠neon
Signed saturating Accumulate of Unsigned value.
vuqadds_s32⚠neon
Signed saturating accumulate of unsigned value
vuzp1_f32⚠neon
Unzip vectors
vuzp1_p8⚠neon
Unzip vectors
vuzp1_p16⚠neon
Unzip vectors
vuzp1_s8⚠neon
Unzip vectors
vuzp1_s16⚠neon
Unzip vectors
vuzp1_s32⚠neon
Unzip vectors
vuzp1_u8⚠neon
Unzip vectors
vuzp1_u16⚠neon
Unzip vectors
vuzp1_u32⚠neon
Unzip vectors
vuzp1q_f32⚠neon
Unzip vectors
vuzp1q_f64⚠neon
Unzip vectors
vuzp1q_p8⚠neon
Unzip vectors
vuzp1q_p16⚠neon
Unzip vectors
vuzp1q_p64⚠neon
Unzip vectors
vuzp1q_s8⚠neon
Unzip vectors
vuzp1q_s16⚠neon
Unzip vectors
vuzp1q_s32⚠neon
Unzip vectors
vuzp1q_s64⚠neon
Unzip vectors
vuzp1q_u8⚠neon
Unzip vectors
vuzp1q_u16⚠neon
Unzip vectors
vuzp1q_u32⚠neon
Unzip vectors
vuzp1q_u64⚠neon
Unzip vectors
vuzp2_f32⚠neon
Unzip vectors
vuzp2_p8⚠neon
Unzip vectors
vuzp2_p16⚠neon
Unzip vectors
vuzp2_s8⚠neon
Unzip vectors
vuzp2_s16⚠neon
Unzip vectors
vuzp2_s32⚠neon
Unzip vectors
vuzp2_u8⚠neon
Unzip vectors
vuzp2_u16⚠neon
Unzip vectors
vuzp2_u32⚠neon
Unzip vectors
vuzp2q_f32⚠neon
Unzip vectors
vuzp2q_f64⚠neon
Unzip vectors
vuzp2q_p8⚠neon
Unzip vectors
vuzp2q_p16⚠neon
Unzip vectors
vuzp2q_p64⚠neon
Unzip vectors
vuzp2q_s8⚠neon
Unzip vectors
vuzp2q_s16⚠neon
Unzip vectors
vuzp2q_s32⚠neon
Unzip vectors
vuzp2q_s64⚠neon
Unzip vectors
vuzp2q_u8⚠neon
Unzip vectors
vuzp2q_u16⚠neon
Unzip vectors
vuzp2q_u32⚠neon
Unzip vectors
vuzp2q_u64⚠neon
Unzip vectors
vzip1_f32⚠neon
Zip vectors
vzip1_p8⚠neon
Zip vectors
vzip1_p16⚠neon
Zip vectors
vzip1_s8⚠neon
Zip vectors
vzip1_s16⚠neon
Zip vectors
vzip1_s32⚠neon
Zip vectors
vzip1_u8⚠neon
Zip vectors
vzip1_u16⚠neon
Zip vectors
vzip1_u32⚠neon
Zip vectors
vzip1q_f32⚠neon
Zip vectors
vzip1q_f64⚠neon
Zip vectors
vzip1q_p8⚠neon
Zip vectors
vzip1q_p16⚠neon
Zip vectors
vzip1q_p64⚠neon
Zip vectors
vzip1q_s8⚠neon
Zip vectors
vzip1q_s16⚠neon
Zip vectors
vzip1q_s32⚠neon
Zip vectors
vzip1q_s64⚠neon
Zip vectors
vzip1q_u8⚠neon
Zip vectors
vzip1q_u16⚠neon
Zip vectors
vzip1q_u32⚠neon
Zip vectors
vzip1q_u64⚠neon
Zip vectors
vzip2_f32⚠neon
Zip vectors
vzip2_p8⚠neon
Zip vectors
vzip2_p16⚠neon
Zip vectors
vzip2_s8⚠neon
Zip vectors
vzip2_s16⚠neon
Zip vectors
vzip2_s32⚠neon
Zip vectors
vzip2_u8⚠neon
Zip vectors
vzip2_u16⚠neon
Zip vectors
vzip2_u32⚠neon
Zip vectors
vzip2q_f32⚠neon
Zip vectors
vzip2q_f64⚠neon
Zip vectors
vzip2q_p8⚠neon
Zip vectors
vzip2q_p16⚠neon
Zip vectors
vzip2q_p64⚠neon
Zip vectors
vzip2q_s8⚠neon
Zip vectors
vzip2q_s16⚠neon
Zip vectors
vzip2q_s32⚠neon
Zip vectors
vzip2q_s64⚠neon
Zip vectors
vzip2q_u8⚠neon
Zip vectors
vzip2q_u16⚠neon
Zip vectors
vzip2q_u32⚠neon
Zip vectors
vzip2q_u64⚠neon
Zip vectors