🔬This is a nightly-only experimental API. (
stdsimd
#48556)Available on RISC-V RV64 and (RISC-V RV32 or RISC-V RV64) only.
Expand description
Stores virtual machine memory by half integer
This instruction performs an explicit memory access as though V=1
;
i.e., with the address translation and protection, and the endianness, that apply to memory
accesses in either VS-mode or VU-mode.
This function is unsafe for it accesses the virtual supervisor or user via a HSV.H
instruction which is effectively a dereference to any memory address.